JP2013219311A - 半導体装置及びその製造方法 - Google Patents
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- 239000010941 cobalt Substances 0.000 claims description 14
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Abstract
【解決手段】半導体装置1は、半導体基板2と、半導体基板2の主面に対して垂直に設けられた半導体ピラー6aと、半導体基板2の主面に対して垂直に設けられ、かつ少なくとも上面が絶縁体である絶縁体ピラー6cと、半導体ピラー6aの側面を覆うゲート絶縁膜9と、ゲート絶縁膜9を介して半導体ピラー6aの側面を覆うゲート電極12aと、絶縁体ピラー6cの側面を覆い、かつゲート電極12aと一体に構成される延長ゲート電極12cと、絶縁体ピラー6cの上面に形成され、かつ該上面の外周の少なくとも一部で延長ゲート電極12cと接触する導電膜20とを備える。
【選択図】図1
Description
2 半導体基板
4,4a,4b,7 シリコン酸化膜
5,15,31 シリコン窒化膜
6a 第1の半導体ピラー
6b 第2の半導体ピラー
6c,6d 絶縁体ピラー
8 下部拡散層
9 ゲート絶縁膜
10 バリア層
11 ポリシリコン膜
12 ゲート電極
12a 第1のゲート電極
12b 第2のゲート電極
12c 延長ゲート電極
13,21 層間絶縁膜
14 マスクシリコン酸化膜
16 部拡散層
17 LDD拡散層
18,22b,23b,24b バリア層
19,22a,23a,24a タングステン膜
20 導電膜
22,221,222,223,224,225,226 下部拡散層コンタクトプラグ
22c コバルトシリサイド膜
23,231,232,233,234,235,236 上部拡散層コンタクトプラグ
24,2412,2434,2456 ゲートコンタクトプラグ
25 配線パターン
30 パッド酸化膜
32 サイドウォール酸化膜
33 サイドウォール窒化膜
34 非晶質シリコン膜
40,41 溝
42,43a,43b 開口部
44〜46 コンタクトホール
Ka,Kb,K 活性領域
Tra,Trb,Tr1〜Tr6 トランジスタ
Claims (23)
- 半導体基板と、
前記半導体基板の主面に対して垂直に設けられた第1の半導体ピラーと、
前記半導体基板の主面に対して垂直に設けられ、かつ少なくとも上面が絶縁体である絶縁体ピラーと、
前記第1の半導体ピラーの側面を覆うゲート絶縁膜と、
前記ゲート絶縁膜を介して前記第1の半導体ピラーの側面を覆う第1のゲート電極と、
前記絶縁体ピラーの側面を覆い、かつ前記第1のゲート電極と一体に構成される延長ゲート電極と、
前記絶縁体ピラーの上面に形成され、かつ該上面の外周の少なくとも一部で前記延長ゲート電極と接触する導電膜と
を備えることを特徴とする半導体装置。 - 前記導電膜は、金属材料によって構成される
ことを特徴とする請求項1に記載の半導体装置。 - 前記導電膜は、第1のバリア層の上に金属材料が積層された構造を有する積層膜である
ことを特徴とする請求項2に記載の半導体装置。 - 前記金属材料はタングステンである
ことを特徴とする請求項2又は3に記載の半導体装置。 - 前記導電膜は、不純物ドープシリコン膜と比べて小さな抵抗率を有する材料によって構成される
ことを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置。 - 前記導電膜は、前記絶縁体ピラーの上面の全周で前記延長ゲート電極と接触するよう構成される
ことを特徴とする請求項1乃至5のいずれか一項に記載の半導体装置。 - 前記ゲート電極及び前記延長ゲート電極はそれぞれ、第2のバリア層の上にポリシリコンが積層された構造を有する積層膜である
ことを特徴とする請求項1乃至6のいずれか一項に記載の半導体装置。 - 前記第1の半導体ピラー、前記絶縁体ピラー、前記第1のゲート電極、前記延長ゲート電極、及び前記導電膜の上から前記半導体基板の主面を覆う層間絶縁膜と、
前記第1の半導体ピラーの下部に接して設けられた下部拡散層と、
前記第1の半導体ピラーの上部に接して設けられた上部拡散層と、
前記層間絶縁膜を貫通し、かつ底面で前記下部拡散層と電気的に接触する下部拡散層コンタクトプラグと、
前記層間絶縁膜を貫通し、かつ底面で前記上部拡散層と電気的に接触する上部拡散層コンタクトプラグと、
前記層間絶縁膜を貫通し、かつ底面で前記延長ゲート電極及び前記導電膜のいずれか少なくとも一方と電気的に接触するゲートコンタクトプラグと
をさらに備えることを特徴とする請求項1乃至7のいずれか一項に記載の半導体装置。 - 前記導電膜は前記上部拡散層の上面にも形成され、
前記上部拡散層コンタクトプラグは、前記導電膜を介して、前記上部拡散層と電気的に接触する
ことを特徴とする請求項8に記載の半導体装置。 - 前記下部拡散層コンタクトプラグはコバルトシリサイド膜を有し、該コバルトシリサイド膜により前記下部拡散層と接触する
ことを特徴とする請求項8又は9に記載の半導体装置。 - 前記半導体基板の主面に対して垂直に設けられた第2の半導体ピラーをさらに備え、
前記絶縁体ピラーは、前記第1及び第2の半導体ピラーの間に設けられ、
前記ゲート絶縁膜は、前記第2の半導体ピラーの側面をさらに覆い、
前記半導体装置は、前記ゲート絶縁膜を介して前記第2の半導体ピラーの側面を覆う第2のゲート電極をさらに備え、
前記延長ゲート電極は、前記第1及び第2のゲート電極と一体に構成される
ことを特徴とする請求項1乃至10のいずれか一項に記載の半導体装置。 - 前記半導体基板の主面は、それぞれ素子分離領域によって区画された第1及び第2の活性領域を有し、
前記第1の半導体ピラーは前記第1の活性領域内に設けられ、
前記第2の半導体ピラーは前記第2の活性領域内に設けられる
ことを特徴とする請求項11に記載の半導体装置。 - 前記半導体基板の主面は、素子分離領域によって区画された第3の活性領域を有し、
前記第1及び第2の半導体ピラーはともに前記第3の活性領域内に設けられる
ことを特徴とする請求項12に記載の半導体装置。 - 半導体基板の主面に、半導体ピラーと、少なくとも上面が絶縁体である絶縁体ピラーとを立設するステップと、
前記半導体ピラーの側面にゲート絶縁膜を形成するステップと、
前記ゲート絶縁膜を介して前記半導体ピラーの側面を覆うゲート電極と、絶縁体ピラーの側面を覆い、かつ前記ゲート電極と一体に構成される延長ゲート電極とを形成するステップと、
前記絶縁体ピラーの上面に、該上面の外周の少なくとも一部で前記延長ゲート電極と接触する導電膜を形成するステップと
を備えることを特徴とする半導体装置の製造方法。 - 前記半導体ピラー及び前記絶縁体ピラーを立設するステップは、前記半導体基板の主面に形成されたマスク絶縁膜をマスクとして前記半導体基板の主面をエッチングすることにより行い、
前記半導体装置の製造方法は、前記マスク絶縁膜のうち少なくとも前記絶縁体ピラーの上面に形成された部分を除去するステップをさらに備え、
前記導電膜を形成するステップは、前記絶縁体ピラーの上面に形成された前記マスク絶縁膜が除去された後に行われる
ことを特徴とする請求項14に記載の半導体装置の製造方法。 - 前記ゲート電極及び前記延長ゲート電極を形成した後に第2の層間絶縁膜を成膜し、前記マスク絶縁膜の上面が露出するように表面を平坦化するステップをさらに備え、
前記マスク絶縁膜を除去するステップは、前記第2の層間絶縁膜の表面の平坦化後に行われ、
前記導電膜を形成するステップでは、前記マスク絶縁膜が除去されたことによって前記絶縁体ピラーの上面に形成された第1の開口部内に、前記導電膜が形成される
ことを特徴とする請求項15に記載の半導体装置の製造方法。 - 前記マスク絶縁膜を除去するステップでは、前記マスク絶縁膜のうち少なくとも前記半導体ピラーの上面に形成された部分も除去され、
前記導電膜を形成するステップでは、前記マスク絶縁膜が除去されたことによって前記半導体ピラーの上面に形成された第2の開口部内にも、前記導電膜が形成される
ことを特徴とする請求項16に記載の半導体装置の製造方法。 - 前記第1及び第2の開口部の内壁を覆うサイドウォール絶縁膜を形成するステップと、
前記サイドウォール絶縁膜を形成した後、前記半導体ピラーの上面に上部拡散層を形成するステップと、
前記第2の開口部内の前記サイドウォール絶縁膜が前記ゲート電極の上端以上の高さまで残る一方、前記第1の開口部内の前記サイドウォール絶縁膜が除去されるよう、前記サイドウォール絶縁膜をエッチングするステップとをさらに備える
ことを特徴とする請求項17に記載の半導体装置の製造方法。 - 前記導電膜は、金属材料によって構成される
ことを特徴とする請求項14乃至18のいずれか一項に記載の半導体装置の製造方法。 - 前記導電膜を形成するステップでは、バリア層及び金属材料を順次成膜することにより、前記導電膜を形成する
ことを特徴とする請求項19に記載の半導体装置の製造方法。 - 前記金属材料はタングステンである
ことを特徴とする請求項19又は20に記載の半導体装置の製造方法。 - 前記導電膜は、不純物ドープシリコン膜と比べて小さな抵抗率を有する材料によって構成される
ことを特徴とする請求項14乃至21のいずれか一項に記載の半導体装置の製造方法。 - 前記導電膜を覆う第1の層間絶縁膜を前記半導体基板の主面に成膜するステップと、
前記第1の層間絶縁膜を貫通し、かつ底面に前記延長ゲート電極及び前記導電膜のいずれか少なくとも一方が露出したコンタクトホールを穿孔するステップと、
前記コンタクトホール内に導電材料を埋め込むことにより、前記延長ゲート電極及び前記導電膜と電気的に接触するゲートコンタクトプラグを形成するステップと
をさらに備えることを特徴とする請求項14乃至22のいずれか一項に記載の半導体装置の製造方法。
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US20150118833A1 (en) * | 2013-10-24 | 2015-04-30 | Applied Materials, Inc. | Method of making source/drain contacts by sputtering a doped target |
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