JP2013033951A - 半導体装置およびその駆動方法 - Google Patents
半導体装置およびその駆動方法 Download PDFInfo
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- 239000000126 substance Substances 0.000 description 3
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
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- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
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- G11—INFORMATION STORAGE
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
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- H01L21/8232—Field-effect technology
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- H01L21/8232—Field-effect technology
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Abstract
【解決手段】読み出しトランジスタのしきい値の絶対値をビット線のデータ電位の変動幅よりも大きくする(あるいはビット線のデータ電位の変動幅を読み出しトランジスタのしきい値の絶対値よりも小さくする)ことで、ソース線の電位を固定し、また、書き込みワード線の電位変動を小さくでき、読み出しワード線の電位は、読み出しの際にのみ変動させる。また、そのようなしきい値の絶対値の大きなトランジスタは、ゲートの材料を仕事関数の高い窒化インジウム等を用いて形成する。仕事関数の高い材料を用いることで、ゲート絶縁物のポテンシャル障壁が高まり、リーク電流が抑制できるので、電荷保持特性も向上する。
【選択図】図2
Description
図2を用いて、本発明の一態様の半導体メモリ装置の駆動方法の例を説明する。用いるメモリセルの回路は図1に示されるものと同じものである。図3および図4で説明した場合と同様に、ビット線BLの電位をデータに応じて0Vあるいは+1Vとする。本実施の形態では、書き込みトランジスタWTのしきい値を+1V、読み出しトランジスタRTのしきい値を+1.5Vとする。また、以下では、ソース線SLの電位を0Vに固定する。このような高いしきい値を実現するためには、読み出しトランジスタRTのゲートに高仕事関数化合物半導体を用いればよい。
図6および図7を用いて、本発明の一態様の半導体メモリ装置の作製工程について簡単に説明する。詳細は公知の半導体集積回路作製技術あるいは特許文献2あるいは特許文献3を参照するとよい。なお、図6および図7は、作製工程を概念的に説明するもので、特定の断面を表すものではない。
最初に、公知の半導体集積回路作製技術を用いて、半導体の基板101表面に、素子分離絶縁物102、P型ウェル103a、N型ウェル103b、P型ウェル103c、N型不純物領域104a、N型不純物領域104b、P型不純物領域104c、P型不純物領域104d、N型不純物領域104e、N型不純物領域104f、ダミーゲート105a、ダミーゲート105b、ダミーゲート105c、第1層間絶縁物106を形成する。
ダミーゲート105a、ダミーゲート105b、ダミーゲート105cを除去し、空孔107a、空孔107b、空孔107cを形成する。そして、メモリセルの領域にのみ、高仕事関数化合物半導体膜108を形成する。
図6(B)で示した方法と同様にPチャネル型トランジスタを形成する空孔107bには、適切な仕事関数を有する材料により形成された第1金属膜109を形成する。さらに、空孔107a、空孔107b、空孔107cに、Nチャネル型トランジスタに適切で、導電性の高い材料の膜を形成する。
第2層間絶縁物111と、必要によっては第1層間絶縁物106をエッチングして、N型不純物領域104a、N型不純物領域104b、P型不純物領域104c、P型不純物領域104d、第2金属膜110c、N型不純物領域104fに達するコンタクトホールを形成する。
第1層配線113a、第1層配線113b、第1層配線113c、第1層配線113d、第1層配線113eを形成し、これを第1埋め込み絶縁物114に埋め込んだ形状とする。なお、図に示されるように、第1層配線113bは、第1コンタクトプラグ112bと第1コンタクトプラグ112cを接続する。また、第1層配線113d、第1層配線113eは、メモリセルの書き込みトランジスタのソースとドレインとなる。
半導体層115を形成し、これを覆って、ゲート絶縁物116を形成する。半導体層115には、厚さが5nm以下、好ましくは2nm以下のシリコンや、酸化物半導体を用いることもできる。この際、ゲート絶縁物116の物理的な厚さが、半導体層115の物理的な厚さの2倍以上あると、半導体層115をゲート絶縁物116で確実に覆うことができ、配線間ショートを防止できるので好ましい。
第3層間絶縁物118、第2コンタクトプラグ119a、第2コンタクトプラグ119bを形成し、その上に第3層配線120、第4層間絶縁物121を形成する。第3層配線120はビット線である。このようにして半導体メモリ装置を作製できる。
102 素子分離絶縁物
103a P型ウェル
103b N型ウェル
103c P型ウェル
104a N型不純物領域
104b N型不純物領域
104c P型不純物領域
104d P型不純物領域
104e N型不純物領域
104f N型不純物領域
105a ダミーゲート
105b ダミーゲート
105c ダミーゲート
106 第1層間絶縁物
107a 空孔
107b 空孔
107c 空孔
108 高仕事関数化合物半導体膜
109 第1金属膜
110a 第2金属膜
110b 第2金属膜
110c 第2金属膜
111 第2層間絶縁物
112a 第1コンタクトプラグ
112b 第1コンタクトプラグ
112c 第1コンタクトプラグ
112d 第1コンタクトプラグ
112e 第1コンタクトプラグ
112f 第1コンタクトプラグ
113a 第1層配線
113b 第1層配線
113c 第1層配線
113d 第1層配線
113e 第1層配線
114 第1埋め込み絶縁物
115 半導体層
116 ゲート絶縁物
117a 第2層配線
117b 第2層配線
117c 第2層配線
118 第3層間絶縁物
119a 第2コンタクトプラグ
119b 第2コンタクトプラグ
120 第3層配線
121 第4層間絶縁物
BL ビット線
RWL 読み出しワード線
WWL 書き込みワード線
SL ソース線
WT 書き込みトランジスタ
RT 読み出しトランジスタ
SC 保持容量
SN 保持ノード
GE ゲート
GI ゲート絶縁物
CH チャネルの形成される領域
SR ソース
DR ドレイン
Claims (9)
- 書き込みワード線と、読み出しワード線と、ビット線と、ソース線と、書き込みトランジスタと、読み出しトランジスタと、キャパシタを有し、
前記書き込みトランジスタのソースと前記読み出しトランジスタのゲートと前記キャパシタの電極の一とが接続し、
前記書き込みトランジスタのゲートは前記書き込みワード線に接続し、
前記書き込みトランジスタのドレインと前記読み出しトランジスタのドレインは前記ビット線に接続し、
前記読み出しトランジスタのソースは前記ソース線に接続し、
前記読み出しトランジスタのしきい値の絶対値は、前記ビット線のデータ電位の変動幅よりも大きいことを特徴とする半導体装置。 - 書き込みワード線と、読み出しワード線と、ビット線と、
ソース線と、Nチャネル型の書き込みトランジスタと、読み出しトランジスタと、キャパシタを有し、
前記書き込みトランジスタのソースと前記読み出しトランジスタのゲートと前記キャパシタの電極の一とが接続し、
前記書き込みトランジスタのゲートは前記書き込みワード線に接続し、
前記書き込みトランジスタのドレインと前記読み出しトランジスタのドレインは前記ビット線に接続し、
前記読み出しトランジスタのソースは前記ソース線に接続し、
前記読み出しトランジスタのゲートには仕事関数が5.2電子ボルト以上の材料を用いることを特徴とする半導体装置。 - 請求項1あるいは請求項2において、前記読み出しトランジスタのゲートにはインジウムあるいは亜鉛の少なくとも一つと窒素を有する化合物が用いられることを特徴とする半導体装置。
- 請求項1乃至請求項3のいずれかにおいて、前記ビット線の最低電位から前記書き込みワード線の最低電位を差し引いた値は0.5V以上であることを特徴とする半導体装置。
- 請求項1乃至請求項4のいずれかにおいて、前記書き込みトランジスタは酸化物半導体を用いて形成されることを特徴とする半導体装置。
- 請求項1乃至請求項5のいずれかにおいて、前記書き込みトランジスタはバンドギャップが2.5電子ボルト以上の半導体を用いて形成されることを特徴とする半導体装置。
- 請求項1乃至請求項6のいずれかにおいて、前記読み出しトランジスタは単結晶シリコンを用いて形成されることを特徴とする半導体装置。
- 書き込みワード線と、読み出しワード線と、ビット線と、ソース線と、書き込みトランジスタと、読み出しトランジスタと、キャパシタを有し、
前記書き込みトランジスタのソースと前記読み出しトランジスタのゲートと前記キャパシタの電極の一とが接続し、
前記書き込みトランジスタのゲートは前記書き込みワード線に接続し、
前記書き込みトランジスタのドレインと前記読み出しトランジスタのドレインは前記ビット線に接続し、
前記読み出しトランジスタのソースは前記ソース線に接続する半導体装置において、
前記ビット線のデータ電位の変動幅を前記読み出しトランジスタのしきい値の絶対値よりも小さくすることを特徴とする半導体装置の駆動方法。 - 請求項8において、前記ソース線の電位を固定することを特徴とする半導体装置の駆動方法。
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