JP2013008771A - 半導体モジュール - Google Patents
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Abstract
【解決手段】半導体チップ11と接合する側の実装基材13の面に凹凸部131が形成され、この凹凸部131は、接合材12を介して半導体チップ11と実装基材13とが接合された際に、半導体チップ11の電極部と実装基材13との接合面の端部を跨ぐように配置され、半導体チップ11と実装基材13とは、凹凸部131の凸部頂点で最も近接していることを特徴とする。
【選択図】図1
Description
図1は本発明の実施形態1に係る半導体モジュールの構成を示す図であり、同図(a)は平面図、同図(b)は断面図である。
図5は本発明の実施形態2に係る半導体モジュールの構成を示す断面図である。この実施形態2において、先の実施形態1と異なる点は、半導体チップ11にも凹凸部111を設けたことである。図5(a)に示す構成では、半導体チップ11の実装基材13との接合面に凹凸部111を設け、半導体チップ11の外周の実装基材13に先の実施形態1と同様の凹凸部131を設けている。
図5(b)に示す構成では、先の同図(a)に示す構成に対して、半導体チップ11の中央部に対向した実装基材13の接合面に凹凸部131を加えたものである。このような構成により、先の図5(a)の構成で得られる効果に対して、接合材12の平均厚さをより一層低減して熱抵抗を低減することが可能となり、この結果、より一層冷却性能を向上することができる。
図6は本発明の実施形態3に係る半導体モジュールの構成を示す断面図であり、同図(a)は接合前の各部材の断面図であり、同図(b)は接合後の各部材の断面図である。
図9は本発明の実施形態4に係る半導体モジュールの構成を示す断面図である。
12…接合材
13…実装基材
61…凹凸部材
91,92…電極材
111,112,131,131−1,131−2,911…凹凸部
611〜616,1311〜1314…凸部
Claims (8)
- 接合部材を介して実装基材に半導体チップが実装された半導体モジュールにおいて、
前記実装基材における前記半導体チップと接合する側の面と前記半導体チップにおける前記実装基材と接合する側の面の一方または双方に凹凸が形成され、前記凹凸は、前記半導体チップと前記実装基材とが接合された際に、前記半導体チップの電極部と前記実装基材との接合面の端部を跨ぐように配置され、前記実装基材と前記半導体チップとは、前記凹凸の凸部頂点で最も近接している
ことを特徴とする半導体モジュール。 - 前記半導体チップにおける、前記実装基材が接合される面と反対の面に電極材が電気的に接合され、前記電極材における前記半導体チップと接合する側の面と前記半導体チップにおける前記電極材と接合する側の面の一方または双方に凹凸が形成され、前記凹凸は、前記半導体チップと前記電極材とが接合された際に、前記半導体チップの電極部と前記電極材との接合面の端部を跨ぐように配置され、前記電極材と前記半導体チップとは、前記凹凸の凸部頂点で最も近接している
ことを特徴とする請求項1に記載の半導体モジュール。 - 接合部材を介して実装基材に半導体チップが実装された半導体モジュールにおいて、
前記実装基材と前記半導体チップとの間に凹凸部材を有し、前記凹凸部材は、前記凹凸部材を介在させて前記半導体チップと前記実装基材とが接合された際に、前記半導体チップの電極部と前記実装基材との接合面の端部を跨ぐように配置され、前記凹凸部材と前記半導体チップとは、前記凹凸部材の凸部頂点で最も近接している
ことを特徴とする半導体モジュール。 - 前記半導体チップにおける、前記実装基材が接合される面と反対の面に電極材が電気的に接合され、前記電極材と前記半導体チップとの間に凹凸部材を有し、前記凹凸部材は、前記凹凸部材を介在させて前記半導体チップと前記電極材とが接合された際に、前記半導体チップの電極部と前記電極材との接合面の端部を跨ぐように配置され、前記凹凸部材と前記半導体チップとは、前記凹凸部材の凸部頂点で最も近接している
ことを特徴とする請求項3に記載の半導体モジュール。 - 前記凹凸または前記凹凸部材は、前記半導体チップと前記実装基材または電極材との接合面に対して傾斜を有する形状である
ことを特徴とする請求項1〜4の何れか1項に記載の半導体モジュール。 - 前記凹凸または前記凹凸部材の凸部頂点は、少なくとも1以上の点または線状に近接している
ことを特徴とする請求項1〜5の何れか1項に記載の半導体モジュール。 - 前記半導体チップと前記実装基材または前記凹凸部材もしくは前記電極材は、前記接合材または直接接合により接合されている
ことを特徴とする請求項1〜6の何れか1項に記載の半導体モジュール。 - 前記凹凸または前記凹凸部材は、前記半導体チップと前記実装基材または前記電極材との接合面における外周の全部または一部に配置形成されている
ことを特徴とする請求項1〜7の何れか1項に記載の半導体モジュール。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2015060916A (ja) * | 2013-09-18 | 2015-03-30 | セイコーインスツル株式会社 | 半導体装置 |
JP2020102493A (ja) * | 2018-12-20 | 2020-07-02 | 京セラ株式会社 | 配線基板および実装構造体 |
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JP2008282834A (ja) * | 2007-05-08 | 2008-11-20 | Fuji Electric Device Technology Co Ltd | 半導体装置の製造方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2015060916A (ja) * | 2013-09-18 | 2015-03-30 | セイコーインスツル株式会社 | 半導体装置 |
JP2020102493A (ja) * | 2018-12-20 | 2020-07-02 | 京セラ株式会社 | 配線基板および実装構造体 |
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