JPWO2019135284A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JPWO2019135284A1
JPWO2019135284A1 JP2019563730A JP2019563730A JPWO2019135284A1 JP WO2019135284 A1 JPWO2019135284 A1 JP WO2019135284A1 JP 2019563730 A JP2019563730 A JP 2019563730A JP 2019563730 A JP2019563730 A JP 2019563730A JP WO2019135284 A1 JPWO2019135284 A1 JP WO2019135284A1
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Prior art keywords
semiconductor chip
semiconductor device
semiconductor
lead frame
pressing member
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JP2019563730A
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JP7006706B2 (ja
Inventor
直弘 大串
直弘 大串
亮司 村井
亮司 村井
貴彦 村上
貴彦 村上
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
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Abstract

放熱材（４）の上に可撓性を有する半導体チップ（６）がはんだ接合されている。押圧部材（９，１１）の先端で半導体チップ（６）を上から押さえつける。これにより、半導体チップ（６）の凸反りを抑制することができる。そして、ボイドがはんだ（７）内に留まるのを防ぐことができるため、半導体装置の放熱性を向上させることができる。

Description

本発明は、半導体装置に関する。
電力用半導体装置において、通電により発生する熱を効率よく逃がすために半導体チップの下面ははんだ、放熱材、絶縁材を介して冷却機構に接続されている。半導体チップの上面はリードフレームとはんだを介して接続されている。
電力用半導体装置の電流大容量化に伴う半導体チップの損失を抑えるために半導体チップの厚みは５０〜１６０μｍ程度と薄い。また、放熱性能を向上させるために半導体チップの面積は大きくなっている。このため、半導体チップが変形して反るという問題がある。この半導体チップの反りを低減させるため、コレットで半導体チップを上から押さえて放熱材にはんだ接合することが提案されている（例えば、特許文献１参照）。
日本特開平９−５１０５８号公報
しかし、リードフレームをチップ上面にはんだ接合する工程などのチップ接合後の加熱工程でチップ下面のはんだが溶け、再び半導体チップが反ってしまうという問題があった。半導体チップが反ることにより半導体チップと放熱材の間のはんだ内にボイドをトラップしてしまい、その状態ではんだが固まってしまう。これにより、半導体装置の放熱性を損なうという問題があった。
本発明は、上述のような課題を解決するためになされたもので、その目的は半導体チップの反りを抑制し、放熱性を向上させることができる半導体装置を得るものである。
本発明に係る半導体装置は、放熱材と、前記放熱材の上にはんだ接合された可撓性を有する半導体チップと、先端で前記半導体チップを上から押さえつける押圧部材とを備えることを特徴とする。
本発明では、押圧部材の先端で半導体チップを上から押さえつける。これにより、半導体チップの凸反りを抑制することができる。そして、ボイドがはんだ内に留まるのを防ぐことができるため、半導体装置の放熱性を向上させることができる。
実施の形態１に係る半導体装置を示す断面図である。 実施の形態１に係る半導体装置のリードフレームの先端を示す斜視図である。 半導体チップの上面を示す平面図である。 比較例に係る半導体装置を示す断面図である。 実施の形態２に係る半導体装置のリードフレームの先端を示す断面図である。 実施の形態２に係る半導体装置のリードフレームの先端を示す斜視図である。 実施の形態３に係る半導体装置のリードフレームの先端を示す側面図である。 実施の形態４に係る半導体装置のリードフレームの先端を示す側面図である。 実施の形態５に係る半導体装置のリードフレームの先端を示す側面図である。 実施の形態６に係る半導体装置のリードフレームの先端を示す側面図である。 実施の形態６に係る半導体装置のリードフレームの先端を示す斜視図である。 実施の形態７に係る半導体装置のリードフレームの先端を示す側面図である。 実施の形態７に係る半導体装置のリードフレームの先端を示す斜視図である。 実施の形態８に係る半導体装置のリードフレームの先端を示す断面図である。 実施の形態９に係る半導体装置のリードフレームの先端を示す断面図である。 実施の形態１０に係る半導体装置を示す断面図である。 実施の形態１０に係る半導体装置を示す平面図である。 実施の形態１１に係る半導体装置を示す平面図である。
実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態１．
図１は、実施の形態１に係る半導体装置を示す断面図である。冷却機構１の上に放熱材２、絶縁材３及び放熱材４が順に配置されている。放熱材４の上にバンプ５を介して半導体チップ６が載せられ、半導体チップ６がはんだ７により放熱材４に接合されている。
半導体チップ６を囲むケース８が放熱材２の上に設けられている。リードフレーム９の先端が半導体チップ６の上面にはんだ１０により接合されている。リードフレーム９の根元はケース８に固定されている。リードフレーム９の先端の下面に突起１１が設けられている。ここでは、突起１１は、リードフレーム９の先端を半導体チップ６側に９０度曲げたものであり、はんだ１０を介さずに直接的に半導体チップ６の上面に接触している。
図２は、実施の形態１に係る半導体装置のリードフレームの先端を示す斜視図である。図３は、半導体チップの上面を示す平面図である。半導体チップ６の上面には、互いに離間したゲート電極１２とエミッタ電極１３が設けられている。半導体チップ６の上面の中央に温度センス回路１４が設けられている。
半導体チップ６の下面には全面にコレクタ電極が形成されるのに対し、上面には電極が無い部分が存在するため、その電極が無い領域１５で半導体チップ６が凸に反る。そこで、リードフレーム９の先端の突起１１で半導体チップ６の上面の電極が無い領域１５を押さえつける。半導体チップ６は、厚みが５０〜１６０μｍで可撓性を有するため、押圧により容易に変形する。
続いて、本実施の形態の効果を比較例と比較して説明する。図４は、比較例に係る半導体装置を示す断面図である。比較例には、半導体チップ６を上から押さえつける突起１１が存在しない。このため、半導体チップ６が反ってしまう。これよりはんだ７内にボイド１６をトラップしてしまい、半導体装置の放熱性を損なう。
これに対して、本実施の形態では、リードフレーム９の先端の突起１１で半導体チップ６を上から押さえつける。これにより、半導体チップ６の凸反りを抑制することができる。そして、ボイドがはんだ７内に留まるのを防ぐことができるため、半導体装置の放熱性を向上させることができる。
実施の形態２．
図５は、実施の形態２に係る半導体装置のリードフレームの先端を示す断面図である。図６は、実施の形態２に係る半導体装置のリードフレームの先端を示す斜視図である。リードフレーム９の先端の突起１１が二股形状であり、温度センス回路１４を避けて半導体チップ６を押さえつける。これにより、温度センス回路１４を保護することができる。
実施の形態３．
図７は、実施の形態３に係る半導体装置のリードフレームの先端を示す側面図である。リードフレーム９の先端の突起１１が円弧形状である。これにより、リードフレーム９が傾いた状態で半導体チップ６を押さえつける場合でも半導体チップ６が傾くのを防ぐことができる。
実施の形態４．
図８は、実施の形態４に係る半導体装置のリードフレームの先端を示す側面図である。リードフレーム９の先端の突起１１がバネ性を有する形状である。これにより、リードフレーム９の高さのばらつきが大きい場合でも一定荷重で半導体チップ６を押さえることができる。
実施の形態５．
図９は、実施の形態５に係る半導体装置のリードフレームの先端を示す側面図である。突起１１はリードフレーム９とは別パーツであり、Ｓｉ又はＳｉＣなどの半導体チップ６の素材より低硬度の樹脂製である。これにより、半導体チップ６の上面のキズを防ぐことができる。
実施の形態６．
図１０は、実施の形態６に係る半導体装置のリードフレームの先端を示す側面図である。図１１は、実施の形態６に係る半導体装置のリードフレームの先端を示す斜視図である。突起１１と半導体チップ６の間に緩衝材１７が設けられている。緩衝材１７は半導体チップ６の製造時に使用するポリイミドなどの樹脂である。この緩衝材１７によりリードフレーム９と半導体チップ６の擦れを防ぎ、熱サイクルによる半導体チップへのダメージを軽減させることができる。
実施の形態７．
図１２は、実施の形態７に係る半導体装置のリードフレームの先端を示す側面図である。図１３は、実施の形態７に係る半導体装置のリードフレームの先端を示す斜視図である。リードフレーム９の一部はバネ形状９ａである。これにより、半導体チップ６への応力を緩和することができる。
実施の形態８．
図１４は、実施の形態８に係る半導体装置のリードフレームの先端を示す断面図である。リードフレーム９と半導体チップ６との間にバネ性を有するスペーサー１８を設けた状態ではんだ接合されている。このスペーサー１８を介して半導体チップ６を押さえるため、リードフレーム９の高さがばらついても半導体チップ６を均一に押さえることができる。
実施の形態９．
図１５は、実施の形態９に係る半導体装置のリードフレームの先端を示す断面図である。第１のバンプ５ａが半導体チップ６の下面の四隅と放熱材４との間に配置されている。第２のバンプ５ｂが半導体チップ６の下面の中央と放熱材４との間に配置されている。第２のバンプ５ｂの高さを第１のバンプ５ａの高さより低く設定する。これにより、半導体チップ６を押さえつけた際に下凸形状となり、はんだ１０の最薄部の厚みを第２のバンプ５ｂの高さによって保証することができる。その他の構成及び効果は実施の形態１等と同様である。
実施の形態１０．
図１６は、実施の形態１０に係る半導体装置を示す断面図である。図１７は、実施の形態１０に係る半導体装置を示す平面図である。半導体チップ６が複数並べて配置されている。ケース８は、複数の半導体チップ６にそれぞれワイヤ１９で接続される複数の中継端子２０を有する。ケース８に押さえ梁２１が設けられている。実施の形態１等のリードフレーム９の代わりに、押さえ梁２１が半導体チップ６を上から押さえつける押圧部材として機能する。このようなケース８と一体化した押さえ梁２１はケース８の形状変更によって形成することができる。
実施の形態１１．
図１８は、実施の形態１１に係る半導体装置を示す平面図である。複数の半導体チップ６にそれぞれワイヤ接続される複数の中継端子２０がひとかたまりに並べて配置されている。これにより、複数の中継端子２０が２つに分かれて配置された実施の形態１０に比べて中継端子２０間の距離が短くなり、制御基板を小さくできる。その他の構成及び効果は実施の形態１０と同様である。
押さえ梁２１は、複数の中継端子２０のかたまりの両側においてケース８から半導体チップ６に向けて突出する構成となる。この場合、図１８で破線で囲ったように、複数の中継端子２０のリードカット時に刃が入る空間が必要となる。
なお、半導体チップ６は、珪素によって形成されたものに限らず、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成されたものでもよい。ワイドバンドギャップ半導体は、例えば、炭化珪素、窒化ガリウム系材料、又はダイヤモンドである。このようなワイドバンドギャップ半導体によって形成された半導体チップ６は、耐電圧性や許容電流密度が高いため、小型化できる。この小型化された半導体チップ６を用いることで、この半導体チップ６を組み込んだ半導体装置も小型化できる。また、半導体チップ６の耐熱性が高いため、ヒートシンクの放熱フィンを小型化でき、水冷部を空冷化できるので、半導体装置を更に小型化できる。また、半導体チップ６の電力損失が低く高効率であるため、半導体装置を高効率化できる。
４ 放熱材、５ａ 第１のバンプ、５ｂ 第２のバンプ、６ 半導体チップ、７，１０ はんだ、８ ケース、９ リードフレーム（押圧部材）、９ａ バネ形状、１１ 突起（押圧部材）、１２ ゲート電極（電極）、１３ エミッタ電極（電極）、１４ 温度センス回路、１７ 緩衝材、１８ スペーサー、２０ 中継端子、２１ 押さえ梁（押圧部材）

Claims (15)

  1. 放熱材と、
    前記放熱材の上にはんだ接合された可撓性を有する半導体チップと、
    先端で前記半導体チップを上から押さえつける押圧部材とを備えることを特徴とする半導体装置。
  2. 前記半導体チップを囲むケースを更に備え、
    前記押圧部材の根元は前記ケースに固定されていることを特徴とする請求項１に記載の半導体装置。
  3. 前記半導体チップの上面に互いに離間した複数の電極が設けられ、
    前記押圧部材は、前記半導体チップの上面の前記複数の電極が無い領域を押さえつけることを特徴とする請求項１又は２に記載の半導体装置。
  4. 前記押圧部材は、前記半導体チップの上面にはんだ接合されるリードフレームと、前記リードフレームの先端の下面に設けられた突起とを有することを特徴とする請求項１〜３の何れか１項に記載の半導体装置。
  5. 前記半導体チップの前記上面の中央に温度センス回路が設けられ、
    前記突起は二股形状であり、前記温度センス回路を避けて前記半導体チップを押さえつけることを特徴とする請求項４に記載の半導体装置。
  6. 前記突起は円弧形状であることを特徴とする請求項４に記載の半導体装置。
  7. 前記突起はバネ性を有することを特徴とする請求項４に記載の半導体装置。
  8. 前記突起は前記リードフレームとは別パーツであり、前記半導体チップの素材より低硬度の樹脂製であることを特徴とする請求項４〜７の何れか１項に記載の半導体装置。
  9. 前記押圧部材の前記先端と前記半導体チップの間に緩衝材が設けられていることを特徴とする請求項１〜７の何れか１項に記載の半導体装置。
  10. 前記押圧部材の一部はバネ形状であることを特徴とする請求項１〜９の何れか１項に記載の半導体装置。
  11. 前記押圧部材は、先端が前記半導体チップの上面にはんだ接合されるリードフレームと、前記リードフレームと前記半導体チップとの間に設けられたバネ性を有するスペーサーとを有することを特徴とする請求項１又は２に記載の半導体装置。
  12. 前記押圧部材は、前記ケースに設けられた押さえ梁であることを特徴とする請求項２に記載の半導体装置。
  13. 前記半導体チップが複数並べて配置され、
    前記ケースは、複数の前記半導体チップにそれぞれワイヤ接続され、ひとかたまりに並べて配置された複数の中継端子を有し、
    前記押さえ梁は、前記複数の中継端子のかたまりの両側において前記ケースから前記半導体チップに向けて突出していることを特徴とする請求項１２に記載の半導体装置。
  14. 前記半導体チップの下面の四隅と前記放熱材との間に配置された第１のバンプと、
    前記半導体チップの前記下面の中央と前記放熱材との間に配置された第２のバンプとを更に備え、
    前記第２のバンプの高さは前記第１のバンプの高さより低いことを特徴とする請求項１〜１３の何れか１項に記載の半導体装置。
  15. 前記半導体チップはワイドバンドギャップ半導体によって形成されていることを特徴とする請求項１〜１４の何れか１項に記載の半導体装置。
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