JP2012238697A - 半導体装置 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/93—Variable capacitance diodes, e.g. varactors
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- Condensed Matter Physics & Semiconductors (AREA)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
【解決手段】主表面を有する半導体基板SUBと、半導体基板SUBの主表面に形成された1対のソース/ドレイン領域と、1対のソース/ドレイン領域に挟まれる領域上であって、主表面に接するように形成されたゲート絶縁膜AFEと、ゲート絶縁膜AFEの上面に接するように形成されたゲート電極POとを備える。上記1対のソース/ドレイン領域の一方から他方へ向かう方向のゲート電極POの長さは45nm未満である。ゲート絶縁膜AFEは反強誘電体膜を有する。
【選択図】図2
Description
上記半導体装置は、主表面を有する半導体基板と、半導体基板の主表面に形成された1対のソース/ドレイン領域と、1対のソース/ドレイン領域に挟まれる領域上であって、主表面に接するように形成されたゲート絶縁膜と、ゲート絶縁膜の上面に接するように形成されたゲート電極とを備える。上記1対のソース/ドレイン領域の一方から他方へ向かう方向のゲート電極の長さは45nm未満である。ゲート絶縁膜は反強誘電体膜を有する。
(実施の形態1)
まず、本実施の形態としてチップ状態の半導体装置について説明する。
図5(A)に示すグラフの横軸はMISトランジスタのゲート絶縁膜GIの厚み方向に印加される電界Eの強さを示しており、グラフの縦軸はゲート絶縁膜GIの厚み方向における自発分極Pの強さを示している。図5(A)においては電界E、分極Pともにその向きを正または負の値で表わしている。図5(A)における電界Eの値が0および0に近い状態は、図5(B)に示すようにMISトランジスタのソース領域とドレイン領域とに挟まれた領域(1対のLDDとしてのn-領域LNRに挟まれた領域)にチャネルが形成されないOFF状態である。図5(A)における電界Eの値が0から正または負の方向に大きく離れた状態は、図5(C)に示すようにMISトランジスタのソース領域とドレイン領域とに挟まれた領域(1対のLDDとしてのn-領域LNRに挟まれた領域)にチャネルCNLが形成されたON状態である。図5(C)のON状態は、ゲート絶縁膜GIの内部における分極P(図5(A)参照)の絶対値が大きくなることによりゲート絶縁膜GIの下部にチャネルCNLが形成された状態である。
本実施の形態は、実施の形態1と比較して、容量が形成されている点において異なっている。以下、本実施の形態の構成について説明する。
本実施の形態は、実施の形態1と比較して、可変容量が形成されている点において異なっている。以下、本実施の形態の構成について説明する。
Claims (8)
- 主表面を有する半導体基板と、
前記半導体基板の前記主表面に形成された1対のソース/ドレイン領域と、
前記1対のソース/ドレイン領域に挟まれる領域上であって、前記主表面に接するように形成されたゲート絶縁膜と、
前記ゲート絶縁膜の上面に接するように形成されたゲート電極とを備え、
前記1対のソース/ドレイン領域の一方から他方へ向かう方向の前記ゲート電極の長さは45nm未満であり、
前記ゲート絶縁膜は反強誘電体膜を有する、半導体装置。 - 前記ゲート絶縁膜は、Pb(In0.5Nb0.5)O3、NbNaO3、ZrPbO3、TiZrLaPbO3、TiZrPbO3、NH4H2PO4、およびNH4H2AsO4からなる群から選択される少なくとも1つからなる、請求項1に記載の半導体装置。
- 前記ゲート絶縁膜の厚みは2nm以上50nm未満である、請求項1または2に記載の半導体装置。
- 前記ゲート電極の前記長さに対する、前記ゲート絶縁膜および前記ゲート電極を含むゲート部分の厚みのアスペクト比は2以上4未満である、請求項1〜3のいずれかに記載の半導体装置。
- 前記半導体基板の前記主表面に形成される容量用不純物領域と、
前記容量用不純物領域上に形成された容量用誘電体膜と、
前記容量用誘電体膜上に形成され、かつ前記容量用不純物領域との間で容量を形成するための容量用電極とをさらに備え、
前記容量用誘電体膜は反強誘電体膜を有する、請求項1〜4のいずれかに記載の半導体装置。 - 前記容量用誘電体膜は、Pb(In0.5Nb0.5)O3、NbNaO3、ZrPbO3、TiZrLaPbO3、TiZrPbO3、NH4H2PO4、およびNH4H2AsO4からなる群から選択される少なくとも1つからなる、請求項5に記載の半導体装置。
- 前記半導体基板の前記主表面に形成される可変容量用不純物領域と、
前記可変容量用不純物領域上に形成された可変容量用誘電体膜と、
前記可変容量用誘電体膜上に形成され、かつ前記可変容量用不純物領域との間で可変容量を形成するための可変容量用電極とをさらに備え、
前記可変容量用誘電体膜は、反強誘電体膜を有する、請求項1〜6のいずれかに記載の半導体装置。 - 前記可変容量用誘電体膜は、Pb(In0.5Nb0.5)O3、NbNaO3、ZrPbO3、TiZrLaPbO3、TiZrPbO3、NH4H2PO4、およびNH4H2AsO4からなる群から選択される少なくとも1つからなる、請求項7に記載の半導体装置。
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JP2011106256A JP5690207B2 (ja) | 2011-05-11 | 2011-05-11 | 半導体装置 |
US13/461,389 US9331212B2 (en) | 2011-05-11 | 2012-05-01 | Semiconductor device comprising an antiferroelectric gate insulating film |
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JP2011106256A JP5690207B2 (ja) | 2011-05-11 | 2011-05-11 | 半導体装置 |
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Cited By (1)
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WO2021152945A1 (ja) * | 2020-01-30 | 2021-08-05 | ソニーグループ株式会社 | 記憶素子、半導体装置および半導体装置の製造方法 |
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TWI690080B (zh) * | 2016-06-08 | 2020-04-01 | 聯華電子股份有限公司 | 半導體元件 |
DE112018006841T5 (de) * | 2018-01-12 | 2020-10-01 | Intel Corporation | Antiferroelektrische gate-dielektrikum-transistoren und deren herstellungsverfahren |
US11552180B2 (en) | 2018-06-29 | 2023-01-10 | Intel Corporation | Antiferroelectric perovskite gate oxide for transistor applications |
CN109817706A (zh) * | 2019-03-18 | 2019-05-28 | 西安电子科技大学 | ZrO2基反铁电负电容场效应晶体管 |
US11063131B2 (en) * | 2019-06-13 | 2021-07-13 | Intel Corporation | Ferroelectric or anti-ferroelectric trench capacitor with spacers for sidewall strain engineering |
US11502104B2 (en) | 2019-08-15 | 2022-11-15 | Sandisk Technologies Llc | Antiferroelectric memory devices and methods of making the same |
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US20120286342A1 (en) | 2012-11-15 |
JP5690207B2 (ja) | 2015-03-25 |
US9331212B2 (en) | 2016-05-03 |
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