JP2012080006A - グラフェン配線およびその製造方法 - Google Patents
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Abstract
【解決手段】グラフェン配線の製造方法は、絶縁膜13内に、配線溝30を形成し、前記配線溝内の全面に、触媒膜14を形成し、前記配線溝内の前記触媒膜上に、前記配線溝の底面に対して垂直方向に積層された複数のグラフェンシート16a〜16eで構成されるグラフェン層16を形成することを具備する。
【選択図】 図1
Description
以下に、図1乃至図4を用いて、第1の実施形態に係るグラフェン配線について説明する。第1の実施形態は、配線として、配線溝内に形成された触媒膜上に複数のグラフェンを積層する例である。
図1(a)は、第1の実施形態に係るグラフェン配線の断面図を示している。図1(b)は、図1(a)の破線部の拡大図を示している。なお、図1(b)において、後述するキャップ膜18は、省略している。
図2乃至図4は、第1の実施形態に係るグラフェン配線の製造工程の断面図を示している。
上記第1の実施形態によれば、配線溝30内に触媒膜15を充填した後、その触媒膜15上に複数のグラフェンシートからなるグラフェン層16を形成する。すなわち、配線溝30内にグラフェン層16を形成するという制約がない。このため、配線溝30の微細化が進んだとしても、グラフェン層16が量子化伝導特性を有する範囲でグラフェンシートを枚数に制限なく成長させることができ、低抵抗な配線構造を実現することができる。
以下に、図5乃至図7を用いて、第1の実施形態に係るグラフェン配線の変形例について説明する。なお、上記第1の実施形態と同様の点については説明を省略し、異なる点について説明する。
以下に、図8および図9を用いて、第2の実施形態に係るグラフェン配線について説明する。第1の実施形態は、グラフェン層の下面が配線溝30の上面と同程度またはそれよりも高くなるように形成された。これに対し、第2の実施形態は、グラフェン層の下部側(下面側)の一部が配線溝内に形成される例である。なお、第2の実施形態において、上記第1の実施形態と同様の点については説明を省略し、異なる点について説明する。
図8(a)は、第2の実施形態に係るグラフェン配線の断面図を示している。図8(b)は、図8(a)の破線部の拡大図を示している。なお、図8(b)において、後述するキャップ膜18は、省略している。
図9は、第2の実施形態に係るグラフェン配線の製造工程の断面図を示している。
上記第2の実施形態によれば、第1の実施形態と同様の効果を得ることができる。
以下に、図10および図11を用いて、第3の実施形態に係るグラフェン配線について説明する。第3の実施形態は、第2の実施形態の変形例であり、グラフェン層が全て配線溝内に形成される例である。なお、第3の実施形態において、上記各実施形態と同様の点については説明を省略し、異なる点について説明する。
図10は、第3の実施形態に係るグラフェン配線の断面図を示している。
図11は、第3の実施形態に係るグラフェン配線の製造工程の断面図を示している。
上記第3の実施形態によれば、第2の実施形態と同様の効果を得ることができる。
Claims (5)
- 絶縁膜内に、配線溝を形成し、
前記配線溝内に、触媒膜を形成し、
前記配線溝内の前記触媒膜上に、前記配線溝の底面に対して垂直方向に積層された複数のグラフェンシートで構成されるグラフェン層を形成する
ことを具備することを特徴とするグラフェン配線の製造方法。 - 前記グラフェン層の下面は、前記配線溝の上面と同程度の高さであることを特徴とする請求項1に記載のグラフェン配線の製造方法。
- 前記配線溝を形成した後、前記配線溝内の両側面上および底面上に、触媒下地膜を形成することをさらに具備し、
前記グラフェン層の上面は前記配線溝の上面より高く、前記グラフェン層の下面は前記配線溝の上面より低く、
前記グラフェン層の下部側の端部は、前記触媒下地膜に直接接続されることを特徴とする請求項1に記載のグラフェン配線の製造方法。 - 前記配線溝を形成した後、前記配線溝内の両側面および底面上に、触媒下地膜を形成することをさらに具備し、
前記グラフェン層の上面は、前記配線溝の上面と同程度の高さであり、
前記グラフェン層の端部は、前記触媒下地膜に直接接続されることを特徴とする請求項1に記載のグラフェン配線の製造方法。 - 前記触媒膜の形成は、
前記配線溝内および前記配線溝外の全面に、前記触媒膜を形成し、
前記配線溝外の前記触媒膜をCMPにより除去して、前記配線溝内に前記触媒膜を残存させる
ことを含むことを特徴とする請求項1に記載のグラフェンの製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010225777A JP5550515B2 (ja) | 2010-10-05 | 2010-10-05 | グラフェン配線およびその製造方法 |
US13/216,435 US9159615B2 (en) | 2010-10-05 | 2011-08-24 | Graphene interconnection and method of manufacturing the same |
TW100132452A TWI460839B (zh) | 2010-10-05 | 2011-09-08 | 石墨烯(graphene)內連線及其製造方法 |
KR1020110093135A KR101304146B1 (ko) | 2010-10-05 | 2011-09-15 | 그라핀 배선 및 그 제조 방법 |
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JP2010225777A JP5550515B2 (ja) | 2010-10-05 | 2010-10-05 | グラフェン配線およびその製造方法 |
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JP2012080006A true JP2012080006A (ja) | 2012-04-19 |
JP5550515B2 JP5550515B2 (ja) | 2014-07-16 |
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US (1) | US9159615B2 (ja) |
JP (1) | JP5550515B2 (ja) |
KR (1) | KR101304146B1 (ja) |
TW (1) | TWI460839B (ja) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014183210A (ja) * | 2013-03-19 | 2014-09-29 | Toshiba Corp | グラフェン配線 |
JP2014187307A (ja) * | 2013-03-25 | 2014-10-02 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2015061042A (ja) * | 2013-09-20 | 2015-03-30 | 独立行政法人産業技術総合研究所 | 配線構造の製造方法及び配線構造 |
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US9761530B2 (en) | 2014-09-18 | 2017-09-12 | Kabushiki Kaisha Toshiba | Graphene wiring and method for manufacturing the same |
US9659870B2 (en) | 2014-09-18 | 2017-05-23 | Kabushiki Kaisha Toshiba | Wiring and method for manufacturing the same |
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JP2022520702A (ja) * | 2019-04-12 | 2022-04-01 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 積層された導体ライン及び空隙を有する半導体チップ |
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Publication number | Publication date |
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TW201227902A (en) | 2012-07-01 |
KR20120035857A (ko) | 2012-04-16 |
KR101304146B1 (ko) | 2013-09-05 |
JP5550515B2 (ja) | 2014-07-16 |
TWI460839B (zh) | 2014-11-11 |
US20120080661A1 (en) | 2012-04-05 |
US9159615B2 (en) | 2015-10-13 |
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