JP2012054555A - 相補型金属酸化物半導体(cmos)構造物 - Google Patents
相補型金属酸化物半導体(cmos)構造物 Download PDFInfo
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- JP2012054555A JP2012054555A JP2011187435A JP2011187435A JP2012054555A JP 2012054555 A JP2012054555 A JP 2012054555A JP 2011187435 A JP2011187435 A JP 2011187435A JP 2011187435 A JP2011187435 A JP 2011187435A JP 2012054555 A JP2012054555 A JP 2012054555A
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 161
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- 239000002184 metal Substances 0.000 claims abstract description 154
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- 239000000126 substance Substances 0.000 claims description 10
- 229910052715 tantalum Inorganic materials 0.000 claims description 10
- 229910019001 CoSi Inorganic materials 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
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- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 239000006117 anti-reflective coating Substances 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910052797 bismuth Inorganic materials 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 229910021340 platinum monosilicide Inorganic materials 0.000 claims description 3
- 229910052716 thallium Inorganic materials 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- 229910021193 La 2 O 3 Inorganic materials 0.000 claims description 2
- 229910002367 SrTiO Inorganic materials 0.000 claims description 2
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 2
- 238000001465 metallisation Methods 0.000 claims description 2
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- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
【解決手段】形成されるシリサイド金属ゲート相の変化を生じさせるポリSiゲートスタック高さの変化という欠点のないCMOSシリサイド金属ゲート集積化手法が提供される。集積化手法は、プロセスの複雑さ最小限に保ち、それによって、CMOSトランジスタの製造コストを増加させない。
【選択図】なし
Description
半導体基板の上に配置される複数のポリSiゲートを準備する工程であって、各ポリSiゲートはその上部表面に配置される誘電体キャップを備える工程、
半導体基板中にシリサイド化ソース/ドレイン領域を形成する工程、
半導体基板上に平坦化誘電体スタックを形成する工程、
エッチングプロセスを実行して各ポリSiゲートの上部表面を露出する工程、および
各ポリSiゲートを金属シリサイドゲートに変換するサリサイドプロセスを実行する工程。この実施態様では、同じポリSiイオン注入条件の場合、各金属シリサイドゲートは、実質的に同じ高さを有し、同じシリサイド相で構成され、実質的に同じ仕事関数を有する。
ゲート誘電体の表面の上に配置される複数のシリサイド化金属ゲートであって、同じポリSiイオン注入条件の場合、シリサイド金属ゲートのそれぞれは、シリサイド金属ゲートの寸法に関らず、同じシリサイド相で構成され、実質的に同じ高さを有し、実質的に同じ仕事関数を有する。
半導体基板の上に配置される複数のポリSiゲートを備える構造物を準備する工程、
ポリSiゲートおよび半導体基板を備える構造物の上にオプションのキャッピング層とともにシリサイド金属を堆積する工程、
各ポリSiゲートの間でリフローさせることによって、凹形の材料を形成する工程、
ポリSiゲートのそれぞれの上からシリサイド金属およびオプションのキャッピング層を除去する工程、
形成された凹形の材料をリフローによって除去する工程、および
構造物をアニールし、これによって、ポリSiゲートのそれぞれの間にシリサイド接点領域を形成する工程。
半導体基板の上に配置される複数のポリSiゲートを備える構造物を準備する工程、
ポリSiゲートおよび半導体基板を備える構造物の上に金属含有層およびキャッピング層を含む二層層を形成する工程、
半導体基板上に平坦化誘電体を形成する工程、
各ポリSiゲートの上の金属含有層を露出させる工程、
各ポリSiゲートの上から金属含有層を除去する工程、および
構造物をアニールし、これによって、ポリSiゲートのそれぞれの間にシリサイド接点領域を形成する工程。
Claims (52)
- 相補型金属酸化物半導体(CMOS)構造物を作製するための方法であって、
半導体基板の上に配置される複数のポリSiゲートを準備する工程であって、各ポリSiゲートは、その上部表面上に配置される誘電体キャップを備える工程、
前記半導体基板中にシリサイド化ソース/ドレイン領域を形成する工程、
前記半導体基板上に平坦化誘電体スタックを形成する工程、
エッチングプロセスを実行して各ポリSiゲートの上部表面を露出させる工程、および
各ポリSiゲートを金属シリサイドゲートに変換するサリサイドプロセスを実行する工程
を含み、同じポリSiイオン注入条件の場合に、各金属シリサイドゲートは、実質的に同じ高さを有し、同じシリサイド相で構成され、実質的に同じ仕事関数を有する方法。 - 前記複数のポリSiゲートは、ゲート誘電体の上に形成される、請求項1に記載の方法。
- 前記複数のポリSiゲートは、堆積法、リソグラフィー法およびエッチング法によって形成される、請求項1に記載の方法。
- 前記誘電体キャップは窒化物で構成される、請求項1に記載の方法。
- 前記複数のポリSiゲートを準備する工程は、前記ポリSiゲートの各露出側壁上の少なくとも一つのスペーサの形成を含む、請求項1に記載の方法。
- 前記少なくとも一つのスペーサは、第一のスペーサおよび第二のスペーサを含み、前記第一のスペーサは、前記第二のスペーサより狭い厚さを有する、請求項5に記載の方法。
- シリサイド化ソース/ドレイン領域を形成する工程は、前記半導体基板の上に金属を堆積すること、およびサリサイドプロセスを実行することを含む、請求項1に記載の方法。
- 前記金属は、Ti、Ta、W、Co、Ni、Pt、Pdまたはそれらの合金を含む、請求項7に記載の方法。
- 前記金属は、Co、NiまたはPtである、請求項8に記載の方法。
- 前記サリサイドプロセスは、第一のアニール、選択エッチング工程、およびオプションとして第二のアニールを含む、請求項7に記載の方法。
- 金属堆積の前に、前記半導体基板の上にシリコンの層を形成することをさらに含む、請求項7に記載の方法。
- 平坦化誘電体スタックを形成する前記工程は、堆積および平坦化を含む、請求項1に記載の方法。
- 平坦化誘電体スタックを形成する前記工程は、エッチング停止層を形成すること、中間層誘電体を形成すること、および前記中間層誘電体を平坦化することを含む、請求項1に記載の方法。
- 前記エッチングプロセスは、反応性イオンエッチング工程を含む、請求項1に記載の方法。
- 前記サリサイドプロセスは、各ポリSiゲートの前記少なくとも露出された上部表面の上にブランケットシリサイド金属層を堆積すること、第一のアニールを実行して前記ポリSiゲートの全部または一部を消費させること、未反応シリサイド金属を選択エッチングすること、およびオプションとして第二のアニールを実行することを含む、請求項1に記載の方法。
- 前記シリサイド金属は、Ti、Ta、W、Co、Ni、Pt、Pdまたはそれらの合金を含む、請求項15に記載の方法。
- 前記シリサイド金属は、Co、NiまたはPtである、請求項16に記載の方法。
- 前記第一のアニールは、約350℃から約550℃の温度で実行される、請求項15に記載の方法。
- 前記オプションの第二のアニールは、約600℃から約800℃の温度で実行される、請求項15に記載の方法。
- ゲート誘電体の表面の上に配置される複数のシリサイド化金属ゲートを含むCMOS構造物であって、前記シリサイド化金属ゲートのそれぞれは、同じポリSiイオン注入条件の場合には、前記シリサイド化金属ゲートの寸法に関らず、同じシリサイド相で構成され、実質的に同じ高さを有し、実質的に同じ仕事関数を有するCMOS構造物。
- 前記シリサイド化金属ゲートは、Ti、Ta、W、Co、Ni、Pt、Pdおよびそれらの合金からなる群から選ばれる金属を含む、請求項20に記載のCMOS構造物。
- 前記金属は、Co、NiまたはPtである、請求項21に記載のCMOS構造物。
- 各シリサイド化金属ゲートと前記半導体基板との間に配置されるゲート誘電体をさらに含む、請求項20に記載のCMOS構造物。
- 前記ゲート誘電体は、SiO2、SiOxNy、HfO2、ZrO2、Al2O3、TiO2、La2O3、Y2O3、SrTiO3、LaAlO3、ケイ酸塩類、またはそれらの組み合わせを含む、請求項23に記載のCMOS構造物。
- 各シリサイド化金属ゲートに隣接するシリサイド化ソース/ドレイン領域をさらに含む、請求項20に記載のCMOS構造物。
- 各シリサイド化金属ゲートは、CoSi2、PtSiまたはNiSiを含む、請求項20に記載のCMOS構造物。
- 前記シリサイド化金属ゲートのそれぞれの側壁上に少なくとも一つのスペーサが配置される、請求項20に記載のCMOS構造物。
- 前記少なくとも一つのスペーサは、第一の狭いスペーサおよび第二のより広いスペーサを備える、請求項27に記載のCMOS構造物。
- 前記シリサイドゲートは、As、P、B、Sb、Bi、In、Al、Ga、Tlおよびそれらの混合物からなる群から選ばれるドーパントを含み、前記ドーパントは、前記シリサイド化金属ゲートの仕事関数を変化させる、請求項20に記載のCMOS構造物。
- シリサイド接点を有するCMOS構造物を形成する方法であって、前記方法は、
半導体基板の上に配置される複数のポリSiゲートを備える構造物を準備する工程、
前記ポリSiゲートおよび前記半導体基板を備える前記構造物の上にシリサイド金属を堆積する工程、
各ポリSiゲートの間に凹形のリフロー材料を形成する工程、
前記ポリSiゲートのそれぞれの上からシリサイド金属を除去する工程、
前記凹形のリフロー材料を除去する工程、および
前記構造物をアニールし、これによって、前記ポリSiゲートのそれぞれの間にシリサイド接点領域を形成する工程
を含む方法。 - 前記シリサイド金属は、Ti、Ta、W、Co、Ni、Pt、Pdまたはそれらの合金を含む、請求項30に記載の方法。
- 前記金属は、Co、NiまたはPtである、請求項31に記載の方法。
- 前記凹形のリフロー材料は、反射防止コーティングまたはスピンオン誘電体を含む、請求項30に記載の方法。
- 前記凹形のリフロー材料を形成する工程は、堆積およびオプションのエッチングを含む、請求項30に記載の方法。
- 前記シリサイド金属を除去する工程は、ウェットエッチングプロセスを含む、請求項30に記載の方法。
- 前記アニールする工程は、約300℃から約600℃の温度で実行される第一のアニールする工程を少なくとも含む、請求項30に記載の方法。
- 約600℃から約800℃の温度で実行されるオプションの第二のアニールする工程をさらに含む、請求項36に記載の方法。
- SiO2およびSi3N4を含むキャッピング二層を堆積し、平坦化することによってシリサイド金属ゲートを形成する工程、オプションのウェットエッチングプロセスを実行してSiO2を除去する工程、選択RIEプロセスを実行して前記ゲートの上のSi3N4を除去する工程、前記ゲート上にシリサイド金属を形成する工程、およびサリサイドプロセスを実行する工程をさらに含む、請求項30に記載の方法。
- シリサイド接点を有するCMOS構造物を形成する方法であって、
半導体基板の上に配置される複数のポリSiゲートを備える構造物を準備する工程、
前記ポリSiゲートおよび前記半導体基板を備える前記構造物の上に金属含有層およびキャッピング層を備える二層を形成する工程、
前記半導体基板上に平坦化材料を形成する工程、
各ポリSiゲートの上で前記金属含有層を露出させる工程、
各ポリSiゲートの上から前記金属含有層を除去する工程、
前記平坦化材料を平坦化する工程、および
前記構造物をアニールし、これによって、前記ポリSiゲートのそれぞれの間にシリサイド接点領域を形成する工程
を含む方法。 - 前記金属含有層は、Ti、Ta、W、Co、Ni、Pt、Pdまたはそれらの合金を含む、請求項39に記載の方法。
- 前記金属含有層は、Co、NiまたはPtである、請求項40に記載の方法。
- 前記キャッピング層は、TiN、WまたはTiを含む、請求項39に記載の方法。
- 前記平坦化材料は、フォトレジストまたは低温度酸化物を含む、請求項39に記載の方法。
- 前記露出させる工程は、前記平坦化材料の化学機械研摩および前記キャッピング層のエッチングを含む、請求項39に記載の方法。
- 各ポリSiゲートの上からの前記金属含有シリサイド金属の前記除去工程は、ウェットエッチングプロセスを含む、請求項39に記載の方法。
- 前記アニールする工程は、約300℃から約600℃の温度で実行される第一のアニールする工程を少なくとも含む、請求項39に記載の方法。
- 約600℃から約800℃の温度で実行されるオプションの第二のアニールする工程をさらに含む、請求項46に記載の方法。
- SiO2およびSi3N4を含むキャッピング二層を堆積し、平坦化することによってシリサイド金属ゲートを形成する工程、オプションのウェットエッチングプロセスを実行してSiO2を除去する工程、選択RIEプロセスを実行して前記ゲートの上のSi3N4を除去する工程、前記ゲート上にシリサイド金属を形成する工程、およびサリサイドプロセスを実行する工程を含む、請求項39に記載の方法。
- ゲート誘電体の表面の上に配置される複数のポリSiゲート
を含むCMOS構造物であって、前記ポリSiゲートのそれぞれは、前記ポリシリコンゲートと、各ポリSiゲートの間に配置されるシリサイド接点との寸法に関らず、実質的に同じ高さを有するCMOS構造物。 - 前記ポリSiゲートは、As、P、B、Sb、Bi、In、Al、Ga、Tlおよびそれらの混合物からなる群から選ばれるドーパントを含む、請求項49に記載のCMOS構造物。
- 前記シリサイド接点は、NiSi、CoSi2またはPtSiを含む、請求項49に記載のCMOS構造物。
- 前記シリサイド接点は、各ポリSiゲートの側壁上に配置されるスペーサの外部エッジと自己整合される、請求項49に記載のCMOS構造物。
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Also Published As
Publication number | Publication date |
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CN1943027B (zh) | 2010-09-29 |
EP1726041A2 (en) | 2006-11-29 |
WO2005083780A2 (en) | 2005-09-09 |
CN1943027A (zh) | 2007-04-04 |
US7056782B2 (en) | 2006-06-06 |
US7655557B2 (en) | 2010-02-02 |
TWI338349B (en) | 2011-03-01 |
US20080254622A1 (en) | 2008-10-16 |
KR20060132673A (ko) | 2006-12-21 |
JP4917012B2 (ja) | 2012-04-18 |
US20050186747A1 (en) | 2005-08-25 |
TW200531216A (en) | 2005-09-16 |
JP5574441B2 (ja) | 2014-08-20 |
WO2005083780A3 (en) | 2005-12-08 |
US7411227B2 (en) | 2008-08-12 |
JP2007524252A (ja) | 2007-08-23 |
US20060189061A1 (en) | 2006-08-24 |
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