JP5400913B2 - シリサイド化金属ゲートの形成のための方法 - Google Patents
シリサイド化金属ゲートの形成のための方法 Download PDFInfo
- Publication number
- JP5400913B2 JP5400913B2 JP2012032905A JP2012032905A JP5400913B2 JP 5400913 B2 JP5400913 B2 JP 5400913B2 JP 2012032905 A JP2012032905 A JP 2012032905A JP 2012032905 A JP2012032905 A JP 2012032905A JP 5400913 B2 JP5400913 B2 JP 5400913B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- metal
- layer
- dielectric
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 203
- 229910052751 metal Inorganic materials 0.000 title claims description 105
- 239000002184 metal Substances 0.000 title claims description 105
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 84
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 81
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 78
- 229920002120 photoresistant polymer Polymers 0.000 claims description 71
- 239000004020 conductor Substances 0.000 claims description 56
- 229920005591 polysilicon Polymers 0.000 claims description 56
- 239000000463 material Substances 0.000 claims description 48
- 239000004065 semiconductor Substances 0.000 claims description 44
- 239000000758 substrate Substances 0.000 claims description 41
- 238000000137 annealing Methods 0.000 claims description 36
- 125000006850 spacer group Chemical group 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 13
- 229910005883 NiSi Inorganic materials 0.000 claims description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- 229910019001 CoSi Inorganic materials 0.000 claims description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 112
- 238000001459 lithography Methods 0.000 description 23
- 238000010586 diagram Methods 0.000 description 13
- 238000001312 dry etching Methods 0.000 description 12
- 238000005137 deposition process Methods 0.000 description 11
- 238000002955 isolation Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 9
- 238000001020 plasma etching Methods 0.000 description 9
- 229910052759 nickel Inorganic materials 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 7
- 229910052697 platinum Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000000654 additive Substances 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 230000000996 additive effect Effects 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052763 palladium Inorganic materials 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 238000005275 alloying Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000010884 ion-beam technique Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000012044 organic layer Substances 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 238000009834 vaporization Methods 0.000 description 3
- 230000008016 vaporization Effects 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000000224 chemical solution deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052914 metal silicate Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052716 thallium Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
- H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
- H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
少なくとも一つのパターン形成されたゲート・スタックを上に備える構造物の上に共形誘電体層と平坦化誘電体層とを含む材料スタックを堆積する工程と、
共形誘電体層と平坦化誘電体層との一部を除去して前記誘電体キャップを露出する工程と、
誘電体キャップを除去してポリシリコン・ゲート導体を露出する工程と、
ポリシリコン・ゲート導体を完全シリサイド化金属ゲートに変換する工程と、
前記ソース領域およびドレイン領域を露出する工程と、
前記ソース領域およびドレイン領域をサリサイド化して完全シリサイド化金属ゲートより薄い厚さを有するシリサイド化ソース領域およびドレイン領域を形成する工程と、を使用する。
前記少なくとも一つのパターン形成されたゲート・スタックを備える構造物の上にパターン形成されたフォトレジストを形成する工程であって、前記パターン形成されたフォトレジストは前記誘電体キャップを露出する開口部を含む工程と、
ドライ・エッチング・プロセスを利用して誘電体キャップを選択的に除去してポリシリコン・ゲート導体を露出する工程と、
パターン形成されたフォトレジストを除去する工程と、
ポリシリコン・ゲート導体を完全シリサイド化金属ゲートに変換する工程と、
前記ソース領域およびドレイン領域をサリサイド化して、完全シリサイド化金属ゲートより薄い厚さを有するシリサイド化ソース領域およびドレイン領域を形成する工程と、を含む。
少なくとも一つのパターン形成されたゲート・スタックと、隣接するソースおよびドレイン領域とを含む構造物を設ける工程であって、前記少なくとも一つのパターン形成されたゲート・スタックはポリシリコン・ゲート導体と、上にある誘電体キャップと、少なくともポリシリコン・ゲート導体の隣接する側壁の上のスペーサと、を含む工程と、
少なくとも一つのパターン形成されたゲート・スタックを上に備える構造物の上に平坦化材料と、マスク層と、フォトレジストとを含むスタックを堆積する工程と、
スタックをパターン形成して誘電体キャップを露出する工程と、
ドライ・エッチング・プロセスを利用して誘電体キャップを選択的に除去してポリシリコン・ゲート導体を露出する工程と、
スタックを除去する工程と、
ポリシリコン・ゲート導体を完全シリサイド化金属ゲートに変換する工程と、
前記ソースおよびドレイン領域をサリサイド化して、完全シリサイド化金属ゲートより薄い厚さを有するシリサイド化ソース領域およびドレイン領域を形成する工程と、を含む。
Claims (19)
- 金属酸化物半導体構造物を形成する方法であって、
少なくとも一つのパターン形成されたゲート・スタックと、当該ゲート・スタックに隣接するソース領域およびドレイン領域とを備える構造物を設ける工程であって、前記ゲート・スタックは、ポリシリコン・ゲート導体と、当該ゲート導体上にある誘電体キャップと、前記ポリシリコン・ゲート導体の少なくとも側壁の上の誘電体ライナと、前記誘電体ライナの上にあって少なくとも前記ポリシリコン・ゲート導体の側壁に隣接するスペーサとを含む、前記設ける工程と、
前記ゲート・スタックを備える構造物の上に共形誘電体層と平坦化誘電体層とを含む材料のスタックを堆積する工程と、
前記共形誘電体層と平坦化誘電体層との一部を除去して前記誘電体キャップを露出する工程と、
前記露出された誘電体キャップを除去して前記ポリシリコン・ゲート導体を露出する工程と、
前記ポリシリコン・ゲート導体を完全シリサイド化金属ゲートに変換する工程と、
前記ソース領域およびドレイン領域を露出する工程と、
前記ソース領域およびドレイン領域をサリサイド化して、前記完全シリサイド化金属ゲートより薄い厚さを有するシリサイド化ソース領域およびドレイン領域を形成する工程と
を含み、
前記少なくとも一つのパターン形成されたゲート・スタックを囲むようにリフト・オフ層を塗布する工程をさらに含む、前記方法。 - 前記共形誘電体層と前記平坦化誘電体層との前記一部を除去する前記工程は、エッチング・バック・プロセスを含む、請求項1に記載の方法。
- 前記共形誘電体層と前記平坦化誘電体層との前記一部を除去する前記工程は、化学的機械研磨を含む、請求項1に記載の方法。
- 前記露出された誘電体キャップを除去する前記工程はエッチング・プロセスを含む、請求項1に記載の方法。
- 前記エッチング・プロセスは、希釈フッ化水素酸を使用するウェット・エッチングを含む、請求項4に記載の方法。
- 前記ポリシリコン・ゲート導体を変換する前記工程はサリサイド化プロセスを含む、請求項1に記載の方法。
- 前記サリサイド化プロセスは、
ポリシリコンと反応して前記露出されたポリシリコン・ゲート導体の上に金属シリサイドを形成することができる少なくとも一つの金属を形成する工程と、
第一のシリサイド相を形成する第一のアニール工程と、
未反応金属を完全に除去する工程と、
前記第一のシリサイド相を第二のシリサイド相に変換する第二のアニール工程と
を含む、請求項6に記載の方法。 - 前記第一のアニール工程は300℃から600℃の温度で実行される、請求項7に記載の方法。
- 前記第二のアニール工程は600℃から800℃の温度で実行される、請求項7に記載の方法。
- 前記第一のアニール工程および前記第二のアニール工程はHe、Ar、N2またはフォーミング・ガスを含む雰囲気中で実行される、請求項7〜9のいずれか一項に記載の方法。
- 前記完全シリサイド化金属ゲートはNiSiまたはNiSiPtを含み、前記シリサイド化ソース領域およびドレイン領域はCoSi2を含む、請求項1〜10のいずれか一項に記載の方法。
- 前記完全シリサイド化金属ゲートはNiSiまたはNiSiPtを含み、前記シリサイド化ソース領域およびドレイン領域はNiSiを含む、請求項1〜10のいずれか一項に記載の方法。
- 金属酸化物半導体構造物を形成する方法であって、
少なくとも一つのパターン形成されたゲート・スタックと、当該ゲート・スタックに隣接するソース領域およびドレイン領域とを含む構造物を設ける工程であって、前記ゲート・スタックは、ポリシリコン・ゲート導体と、当該ゲート導体上にある誘電体キャップと、少なくとも前記ポリシリコン・ゲート導体に隣接する側壁の上にあるスペーサとを含む、前記設ける工程と、
前記ゲート・スタックを備える前記構造物の上にパターン形成されたフォトレジストを形成する工程であって、前記パターン形成されたフォトレジストは前記誘電体キャップを露出する開口部を含む工程と、
ドライ・エッチング・プロセスを利用して前記露出された誘電体キャップを選択的に除去して前記ポリシリコン・ゲート導体を露出する工程と、
前記パターン形成されたフォトレジストを除去する工程と、
前記ポリシリコン・ゲート導体を完全シリサイド化金属ゲートに変換する工程と、
前記ソース領域およびドレイン領域をサリサイド化して、前記完全シリサイド化金属ゲートより薄い厚さを有するシリサイド化ソース領域およびドレイン領域を形成する工程と
を含み、
前記少なくとも一つのパターン形成されたゲート・スタックを囲むようにリフト・オフ層を塗布する工程をさらに含む、前記方法。 - 前記誘電体キャップを除去する前に、前記パターン形成されたゲート・スタックの上の前記リフト・オフ層の一部を除去する、請求項13に記載の方法。
- 前記誘電体キャップを選択的に除去した後であって、前記ポリシリコン・ゲート導体を完全シリサイド化金属ゲートに変換する前に、リフト・オフ・プロセスを用いて前記リフト・オフ層の上の前記パターン形成されたフォトレジストを除去する、請求項13に記載の方法。
- 前記ポリシリコン・ゲート導体を完全シリサイド化金属ゲートに変換する前記工程は、第一のアニールおよび第二のアニールを含み、これらの二つのアニールの間に行われる選択エッチングを使用しない、請求項15に記載の方法。
- 前記露出された誘電体キャップを選択的に除去する前記工程は、ドライ・エッチング・プロセスを含む、請求項13に記載の方法。
- 前記ポリシリコン・ゲート導体を完全シリサイド化金属ゲートに変換する前記工程は、ポリシリコンと反応して前記露出されたポリシリコン・ゲート導体の上に金属シリサイドを形成することができる少なくとも一つの金属を形成する工程と、第一のシリサイド相を形成する第一のアニール工程と、未反応金属を完全に除去する工程と、前記第一のシリサイド相を第二のシリサイド相に変換する第二のアニール工程とを含む、請求項13に記載の方法。
- 金属酸化物半導体構造物を形成する方法であって、
少なくとも一つのパターン形成されたゲート・スタックと、当該ゲート・スタックに隣接するソース領域およびドレイン領域とを含む構造物を設ける工程であって、前記ゲート・スタックはポリシリコン・ゲート導体と、当該ゲート導体上にある誘電体キャップと、少なくとも前記ポリシリコン・ゲート導体に隣接する側壁の上にあるスペーサとを含む、前記設ける工程と、
前記ゲート・スタックを備える構造物の上に平坦化材料、マスク層およびフォトレジストを含むスタックを堆積する工程と、
前記スタックをパターン形成して前記誘電体キャップを露出する工程と、
ドライ・エッチング・プロセスを利用して前記露出された誘電体キャップを選択的に除去して前記ポリシリコン・ゲート導体を露出する工程と、
前記パターン形成されたスタックを除去する工程と、
前記ポリシリコン・ゲート導体を完全シリサイド化金属ゲートに変換する工程と、
前記ソース領域およびドレイン領域をサリサイド化して完全シリサイド化金属ゲートより薄い厚さを有するシリサイド化ソースおよびドレイン領域を形成する工程と
を含み、前記少なくとも一つのパターン形成されたゲート・スタックを囲むようにリフト・オフ層を塗布する工程をさらに含む、前記方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/885,462 | 2004-07-06 | ||
US10/885,462 US7705405B2 (en) | 2004-07-06 | 2004-07-06 | Methods for the formation of fully silicided metal gates |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007520293A Division JP2008506253A (ja) | 2004-07-06 | 2005-03-10 | シリサイド化金属ゲートの形成のための方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012124519A JP2012124519A (ja) | 2012-06-28 |
JP5400913B2 true JP5400913B2 (ja) | 2014-01-29 |
Family
ID=35540415
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007520293A Pending JP2008506253A (ja) | 2004-07-06 | 2005-03-10 | シリサイド化金属ゲートの形成のための方法 |
JP2012032905A Expired - Fee Related JP5400913B2 (ja) | 2004-07-06 | 2012-02-17 | シリサイド化金属ゲートの形成のための方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007520293A Pending JP2008506253A (ja) | 2004-07-06 | 2005-03-10 | シリサイド化金属ゲートの形成のための方法 |
Country Status (7)
Country | Link |
---|---|
US (2) | US7705405B2 (ja) |
EP (1) | EP1807875A4 (ja) |
JP (2) | JP2008506253A (ja) |
KR (1) | KR100945785B1 (ja) |
CN (1) | CN100461463C (ja) |
TW (1) | TWI364796B (ja) |
WO (1) | WO2006014188A2 (ja) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7271455B2 (en) * | 2004-07-14 | 2007-09-18 | International Business Machines Corporation | Formation of fully silicided metal gate using dual self-aligned silicide process |
US7118997B2 (en) * | 2005-01-28 | 2006-10-10 | International Business Machines Corporation | Implantation of gate regions in semiconductor device fabrication |
US20060183323A1 (en) * | 2005-02-14 | 2006-08-17 | Omnivision Technologies, Inc. | Salicide process using CMP for image sensor |
US7732312B2 (en) * | 2006-01-24 | 2010-06-08 | Texas Instruments Incorporated | FUSI integration method using SOG as a sacrificial planarization layer |
US20070298573A1 (en) * | 2006-06-22 | 2007-12-27 | Chien-Ting Lin | Semiconductor device and method for manufacturing the same |
JP2012253374A (ja) * | 2006-10-11 | 2012-12-20 | Fujitsu Semiconductor Ltd | 半導体装置の製造方法 |
US8652912B2 (en) * | 2006-12-08 | 2014-02-18 | Micron Technology, Inc. | Methods of fabricating a transistor gate including cobalt silicide |
US7704835B2 (en) * | 2006-12-29 | 2010-04-27 | Intel Corporation | Method of forming a selective spacer in a semiconductor device |
US8999786B1 (en) | 2007-03-20 | 2015-04-07 | Marvell International Ltd. | Reducing source contact to gate spacing to decrease transistor pitch |
KR100896862B1 (ko) * | 2007-05-18 | 2009-05-12 | 주식회사 동부하이텍 | 반도체 소자의 제조방법 |
US7829416B2 (en) | 2007-08-07 | 2010-11-09 | Panasonic Corporation | Silicon carbide semiconductor device and method for producing the same |
JP2009182089A (ja) * | 2008-01-30 | 2009-08-13 | Panasonic Corp | 半導体装置の製造方法 |
US7939389B2 (en) * | 2008-04-18 | 2011-05-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
CN102074479B (zh) * | 2009-11-24 | 2012-08-29 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
US8664070B2 (en) | 2009-12-21 | 2014-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | High temperature gate replacement process |
US8133746B2 (en) * | 2010-03-01 | 2012-03-13 | International Business Machines Corporation | Method for semiconductor gate hardmask removal and decoupling of implants |
US8431453B2 (en) * | 2011-03-31 | 2013-04-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure |
US8432002B2 (en) * | 2011-06-28 | 2013-04-30 | International Business Machines Corporation | Method and structure for low resistive source and drain regions in a replacement metal gate process flow |
CN102956504A (zh) * | 2012-10-25 | 2013-03-06 | 上海宏力半导体制造有限公司 | 改善多晶硅耗尽的方法以及mos晶体管 |
JP2014135353A (ja) * | 2013-01-09 | 2014-07-24 | National Institute Of Advanced Industrial & Technology | 半導体装置の製造方法 |
US10276562B2 (en) | 2014-01-07 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with multiple threshold voltage and method of fabricating the same |
US9478631B2 (en) * | 2014-06-04 | 2016-10-25 | Taiwan Semiconductor Manufacturing Company Limited | Vertical-gate-all-around devices and method of fabrication thereof |
US11088030B2 (en) | 2015-12-30 | 2021-08-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
JP6808977B2 (ja) * | 2016-05-30 | 2021-01-06 | セイコーエプソン株式会社 | 流路継手および液体噴射装置 |
JP2017213703A (ja) * | 2016-05-30 | 2017-12-07 | セイコーエプソン株式会社 | 流路継手および液体噴射装置 |
US10290739B2 (en) | 2017-09-29 | 2019-05-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device and method of dielectric layer |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6100173A (en) * | 1998-07-15 | 2000-08-08 | Advanced Micro Devices, Inc. | Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process |
US6312997B1 (en) * | 1998-08-12 | 2001-11-06 | Micron Technology, Inc. | Low voltage high performance semiconductor devices and methods |
JP3168992B2 (ja) * | 1998-09-08 | 2001-05-21 | 日本電気株式会社 | 半導体装置の製造方法 |
US6211000B1 (en) * | 1999-01-04 | 2001-04-03 | Advanced Micro Devices | Method of making high performance mosfets having high conductivity gate conductors |
JP2000252462A (ja) * | 1999-03-01 | 2000-09-14 | Toshiba Corp | Mis型半導体装置及びその製造方法 |
US6620718B1 (en) | 2000-04-25 | 2003-09-16 | Advanced Micro Devices, Inc. | Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device |
US6376320B1 (en) * | 2000-11-15 | 2002-04-23 | Advanced Micro Devices, Inc. | Method for forming field effect transistor with silicides of different thickness and of different materials for the source/drain and the gate |
US6562718B1 (en) * | 2000-12-06 | 2003-05-13 | Advanced Micro Devices, Inc. | Process for forming fully silicided gates |
US6475874B2 (en) * | 2000-12-07 | 2002-11-05 | Advanced Micro Devices, Inc. | Damascene NiSi metal gate high-k transistor |
US20020072231A1 (en) * | 2000-12-08 | 2002-06-13 | United Microelectronics Corp. | Method of forming a self-aligned silicide |
US6518137B2 (en) * | 2001-01-19 | 2003-02-11 | United Microelectronics Corp. | Method for forming steep spacer in a MOS device |
US6555453B1 (en) | 2001-01-31 | 2003-04-29 | Advanced Micro Devices, Inc. | Fully nickel silicided metal gate with shallow junction formed |
KR100399357B1 (ko) * | 2001-03-19 | 2003-09-26 | 삼성전자주식회사 | 코발트 실리사이드를 이용한 반도체 장치 및 그 형성 방법 |
US6686248B1 (en) * | 2001-04-03 | 2004-02-03 | Advanced Micro Devices, Inc. | Method of fabricating a semiconductor device having a MOS transistor with a high dielectric constant material |
JP3485103B2 (ja) * | 2001-04-19 | 2004-01-13 | セイコーエプソン株式会社 | Mos型トランジスタ及びその製造方法 |
JP2004039943A (ja) * | 2002-07-05 | 2004-02-05 | Renesas Technology Corp | 半導体装置の製造方法 |
US6846734B2 (en) * | 2002-11-20 | 2005-01-25 | International Business Machines Corporation | Method and process to make multiple-threshold metal gates CMOS technology |
US20050056881A1 (en) | 2003-09-15 | 2005-03-17 | Yee-Chia Yeo | Dummy pattern for silicide gate electrode |
JP4515077B2 (ja) * | 2003-11-13 | 2010-07-28 | 富士通株式会社 | 半導体装置の製造方法 |
US7148143B2 (en) * | 2004-03-24 | 2006-12-12 | Texas Instruments Incorporated | Semiconductor device having a fully silicided gate electrode and method of manufacture therefor |
US7338888B2 (en) * | 2004-03-26 | 2008-03-04 | Texas Instruments Incorporated | Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same |
US7183187B2 (en) * | 2004-05-20 | 2007-02-27 | Texas Instruments Incorporated | Integration scheme for using silicided dual work function metal gates |
-
2004
- 2004-07-06 US US10/885,462 patent/US7705405B2/en active Active
-
2005
- 2005-03-10 EP EP05725271A patent/EP1807875A4/en not_active Withdrawn
- 2005-03-10 JP JP2007520293A patent/JP2008506253A/ja active Pending
- 2005-03-10 WO PCT/US2005/008009 patent/WO2006014188A2/en active Search and Examination
- 2005-03-10 CN CNB2005800228619A patent/CN100461463C/zh not_active Expired - Fee Related
- 2005-03-10 KR KR1020077000660A patent/KR100945785B1/ko not_active IP Right Cessation
- 2005-07-04 TW TW094122559A patent/TWI364796B/zh active
-
2008
- 2008-10-07 US US12/246,921 patent/US8178433B2/en not_active Expired - Fee Related
-
2012
- 2012-02-17 JP JP2012032905A patent/JP5400913B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2008506253A (ja) | 2008-02-28 |
US20090029515A1 (en) | 2009-01-29 |
KR20070029799A (ko) | 2007-03-14 |
TWI364796B (en) | 2012-05-21 |
WO2006014188A2 (en) | 2006-02-09 |
TW200618119A (en) | 2006-06-01 |
JP2012124519A (ja) | 2012-06-28 |
US20060006476A1 (en) | 2006-01-12 |
CN1981386A (zh) | 2007-06-13 |
US8178433B2 (en) | 2012-05-15 |
US7705405B2 (en) | 2010-04-27 |
EP1807875A2 (en) | 2007-07-18 |
CN100461463C (zh) | 2009-02-11 |
WO2006014188A3 (en) | 2006-11-23 |
EP1807875A4 (en) | 2008-11-19 |
KR100945785B1 (ko) | 2010-03-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5400913B2 (ja) | シリサイド化金属ゲートの形成のための方法 | |
JP4917012B2 (ja) | 相補型金属酸化物半導体(cmos)を形成する方法及びその方法に従い製造されたcmos | |
US10340355B2 (en) | Method of forming a dual metal interconnect structure | |
JP4144884B2 (ja) | Cmosトランジスタの製造方法 | |
US7682968B2 (en) | Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby | |
US10707132B2 (en) | Method to recess cobalt for gate metal application | |
US7473975B2 (en) | Fully silicided metal gate semiconductor device structure | |
US20020001892A1 (en) | Method for fabricating semiconductor device | |
JP4981288B2 (ja) | 半導体装置のシリサイド膜の形成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130827 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20130828 Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130828 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130829 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20131007 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20131007 |
|
RD14 | Notification of resignation of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7434 Effective date: 20131007 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131025 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |