JP2011526080A - 電子基板における同心状ビア - Google Patents
電子基板における同心状ビア Download PDFInfo
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- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
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- 229920001940 conductive polymer Polymers 0.000 description 1
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- 238000004544 sputter deposition Methods 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
- H05K1/0222—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09809—Coaxial layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
Abstract
Description
Claims (20)
- 複数の導電性層を有する電子基板内の多壁信号搬送ビア構造であって、
前記基板の1対の導電性層に結合するための外側ビアであり、前記1対の導電性層間に第1の信号経路を形成する外側ビアと、
前記1対の導電性層に結合するための、前記外側ビア内の内側ビアであり、前記1対の導電性層間に第2の信号経路を形成する内側ビアと、
前記内側ビアおよび前記外側ビア間における誘電体層と、
を具備する多壁信号搬送ビア構造。 - 前記1対の層は外側導電性層である請求項1の多壁信号搬送ビア構造。
- 前記1対の層は内側導電性層である請求項1の多壁信号搬送ビア構造。
- 前記1対の導電性層に結合するための、前記内側ビア内の少なくとも1つの付加ビアであって、前記1対の導電性層の間に他の信号経路を形成する少なくとも1つの付加ビアと、
前記少なくとも1つの付加ビアおよび前記内側ビア間の誘電体層と、
をさらに具備する請求項1の多壁信号搬送ビア構造。 - 外側ビア・トレースおよび内側ビア・トレースを含む接点領域をさらに具備し、前記トレースはパターン化された誘電体層によって分離される請求項1の多壁信号搬送ビア構造。
- 複数の導電性層を有する電子基板であって、
前記基板の1ついの導電性層に結合された外側ビアであり、第1の信号経路を形成する外側ビアと、
前記1対の導電性層に結合された、前記外側ビア内の内側ビアであり、第2の信号経路を形成する内側ビアと、
前記内側ビアおよび前記外側ビア間における誘電体層と、
を具備した多壁信号搬送ビア構造を具備する電子基板。 - 前記1対の層は外側導電性層である請求項6の電子基板。
- 前記1対の層は内側導電性層である請求項6の電子基板。
- 前記多壁信号搬送ビア構造は、
前記内側ビア内に配置されかつ前記1対の導電性層に結合された少なくとも1つの付加ビアであり、他の信号経路を形成する少なくとも1つの付加ビアと、
前記少なくとも1つの付加ビアおよび前記内側ビア間における誘電体層と、
をさらに具備する請求項6の電子基板。 - 前記多壁信号搬送ビア構造は、パターン化された外側ビア・トレースとパターン化された内側ビア・トレースを具備し、前記トレースはパターン化された誘電体層によって分離されている接点領域をさらに具備する請求項6の電子基板。
- 前記電子基板は、プリント回路基板である請求項6の電子基板。
- 前記電子基板は、ビルドアップまたはラミネート基板である請求項6の電子基板。
- 前記多壁信号搬送ビア構造は、差動対信号の信号経路内に組み込まれた請求項6の電子基板。
- 基板内に多壁信号搬送ビア構造を作成する方法であって、
複数の導電性層を具備する電子基板を設けること、
1対の導電性層に結合され、前記1対の導電性層の間に第1の信号経路を形成する第1のビアを形成すること、
前記第1のビア内に第1の誘電体層を堆積すること、
前記第1の誘電体層をパターン化すること、
前記第1のビア内でかつ前記第1の誘電体層を貫通して第2のビアを形成すること、前記第2のビアは前記1対の導電性層に結合されかつ前記1対の導電性層の間に信号経路を形成すること、
を具備する方法。 - 前記第2のビアは、
前記第1のビア内にかつ前記第1の誘電体層を貫通して貫通孔を形成すること、
前記貫通孔内にかつ前記1対の導電性層の各層の一部分上に導電性材料をめっきすること、および
前記1対の導電性層の各層の前記一部分上にめっきされた前記導電性材料をパターン化すること、
を具備する方法によって形成される請求項14の方法。 - 前記1対の導電性層は外側導電性層である請求項14の方法。
- 前記1対の導電性層は内側導電性層である請求項14の方法。
- 前記1対の導電性層の各層上にはんだマスクを堆積することをさらに具備する請求項14の方法。
- 前記第2のビア内に第2の誘電体層を堆積すること、および
前記第2のビア内に、前記1ついの導電性層に結合されかつ前記1対の導電性層間に付加信号経路を形成する付加ビアを形成すること、
をさらに具備する請求項14の方法。 - 最内側ビア内に誘電体材料を堆積すること、および
前記1対の導電性層に結合されかつ他の信号経路を形成する他のビアを前記最内側ビア内に形成すること、
を反復して具備する請求項19の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/163,028 US8273995B2 (en) | 2008-06-27 | 2008-06-27 | Concentric vias in electronic substrate |
US12/163,028 | 2008-06-27 | ||
PCT/US2009/048029 WO2009158286A1 (en) | 2008-06-27 | 2009-06-19 | Concentric vias in electronic substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011526080A true JP2011526080A (ja) | 2011-09-29 |
JP5524203B2 JP5524203B2 (ja) | 2014-06-18 |
Family
ID=41061103
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011516479A Active JP5524203B2 (ja) | 2008-06-27 | 2009-06-19 | 多壁信号搬送ビア構造、多壁信号搬送ビア構造を具備する電子基板及び基板内に多壁信号搬送ビア構造を作成する方法 |
Country Status (9)
Country | Link |
---|---|
US (1) | US8273995B2 (ja) |
EP (1) | EP2313920B1 (ja) |
JP (1) | JP5524203B2 (ja) |
KR (2) | KR20120125675A (ja) |
CN (1) | CN102067305B (ja) |
ES (1) | ES2719532T3 (ja) |
HU (1) | HUE044085T2 (ja) |
TW (1) | TWI404480B (ja) |
WO (1) | WO2009158286A1 (ja) |
Cited By (1)
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JP2012174874A (ja) * | 2011-02-21 | 2012-09-10 | Fujitsu Ltd | プリント配線板の製造方法及びプリント配線板 |
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2009
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- 2009-06-19 JP JP2011516479A patent/JP5524203B2/ja active Active
- 2009-06-19 KR KR1020127028794A patent/KR20120125675A/ko not_active Application Discontinuation
- 2009-06-19 ES ES09770820T patent/ES2719532T3/es active Active
- 2009-06-19 HU HUE09770820A patent/HUE044085T2/hu unknown
- 2009-06-19 KR KR1020117001759A patent/KR101213184B1/ko active IP Right Grant
- 2009-06-19 CN CN2009801235529A patent/CN102067305B/zh active Active
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JP2001168530A (ja) * | 1999-12-13 | 2001-06-22 | Ngk Spark Plug Co Ltd | 配線基板及び配線基板の製造方法 |
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JP7178764B2 (ja) | 2018-10-08 | 2022-11-28 | 中興通訊股▲ふん▼有限公司 | 回路基板、デバイスおよびバイアホール構造の形成方法 |
Also Published As
Publication number | Publication date |
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JP5524203B2 (ja) | 2014-06-18 |
EP2313920B1 (en) | 2019-01-09 |
HUE044085T2 (hu) | 2019-09-30 |
ES2719532T3 (es) | 2019-07-11 |
TWI404480B (zh) | 2013-08-01 |
KR20110020941A (ko) | 2011-03-03 |
US20090321126A1 (en) | 2009-12-31 |
WO2009158286A1 (en) | 2009-12-30 |
KR101213184B1 (ko) | 2012-12-18 |
TW201018343A (en) | 2010-05-01 |
US8273995B2 (en) | 2012-09-25 |
CN102067305A (zh) | 2011-05-18 |
KR20120125675A (ko) | 2012-11-16 |
CN102067305B (zh) | 2013-12-04 |
EP2313920A1 (en) | 2011-04-27 |
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