JP2011512040A - 半導体基板表面処理方法 - Google Patents

半導体基板表面処理方法 Download PDF

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Publication number
JP2011512040A
JP2011512040A JP2010546411A JP2010546411A JP2011512040A JP 2011512040 A JP2011512040 A JP 2011512040A JP 2010546411 A JP2010546411 A JP 2010546411A JP 2010546411 A JP2010546411 A JP 2010546411A JP 2011512040 A JP2011512040 A JP 2011512040A
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JP
Japan
Prior art keywords
substrate
oxide
layer
semiconductor substrate
silicon
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2010546411A
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English (en)
Japanese (ja)
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JP2011512040A5 (https=
Inventor
ラドゥアン カーリド，
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
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Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of JP2011512040A publication Critical patent/JP2011512040A/ja
Publication of JP2011512040A5 publication Critical patent/JP2011512040A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H10P70/15—Cleaning before device manufacture, i.e. Begin-Of-Line process by wet cleaning only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H10P70/12—Cleaning before device manufacture, i.e. Begin-Of-Line process by dry cleaning only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Recrystallisation Techniques (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Element Separation (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
JP2010546411A 2008-02-13 2009-01-23 半導体基板表面処理方法 Withdrawn JP2011512040A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP08290138A EP2091070A1 (en) 2008-02-13 2008-02-13 Semiconductor substrate surface preparation method
PCT/IB2009/000141 WO2009101494A1 (en) 2008-02-13 2009-01-23 Semiconductor substrate surface preparation method

Publications (2)

Publication Number Publication Date
JP2011512040A true JP2011512040A (ja) 2011-04-14
JP2011512040A5 JP2011512040A5 (https=) 2011-09-15

Family

ID=39638664

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010546411A Withdrawn JP2011512040A (ja) 2008-02-13 2009-01-23 半導体基板表面処理方法

Country Status (6)

Country Link
US (1) US8062957B2 (https=)
EP (2) EP2091070A1 (https=)
JP (1) JP2011512040A (https=)
KR (1) KR20100114884A (https=)
CN (1) CN101952934A (https=)
WO (1) WO2009101494A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016540367A (ja) * 2013-09-25 2016-12-22 エーファウ・グループ・エー・タルナー・ゲーエムベーハー 基板をボンディングする装置および方法
JP2020057810A (ja) * 2019-12-23 2020-04-09 エーファウ・グループ・エー・タルナー・ゲーエムベーハー 基板をボンディングする装置および方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4894390B2 (ja) * 2006-07-25 2012-03-14 信越半導体株式会社 半導体基板の製造方法
JP6030455B2 (ja) * 2013-01-16 2016-11-24 東京エレクトロン株式会社 シリコン酸化物膜の成膜方法
JP2015233130A (ja) * 2014-05-16 2015-12-24 株式会社半導体エネルギー研究所 半導体基板および半導体装置の作製方法
US10964664B2 (en) * 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5238865A (en) * 1990-09-21 1993-08-24 Nippon Steel Corporation Process for producing laminated semiconductor substrate
DE69331816T2 (de) * 1992-01-31 2002-08-29 Canon K.K., Tokio/Tokyo Verfahren zur Herstellung eines Halbleitersubstrats
JP3116628B2 (ja) * 1993-01-21 2000-12-11 株式会社日本自動車部品総合研究所 吸着装置
JP2978748B2 (ja) * 1995-11-22 1999-11-15 日本電気株式会社 半導体装置の製造方法
US6007641A (en) * 1997-03-14 1999-12-28 Vlsi Technology, Inc. Integrated-circuit manufacture method with aqueous hydrogen-fluoride and nitric-acid oxide etch
TW460617B (en) 1998-11-06 2001-10-21 United Microelectronics Corp Method for removing carbon contamination on surface of semiconductor substrate
US6709989B2 (en) * 2001-06-21 2004-03-23 Motorola, Inc. Method for fabricating a semiconductor structure including a metal oxide interface with silicon
JP2004266075A (ja) * 2003-02-28 2004-09-24 Tokyo Electron Ltd 基板処理方法
US6911375B2 (en) * 2003-06-02 2005-06-28 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
WO2005027214A1 (ja) 2003-09-10 2005-03-24 Shin-Etsu Handotai Co., Ltd. 積層基板の洗浄方法及び基板の貼り合わせ方法並びに貼り合せウェーハの製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016540367A (ja) * 2013-09-25 2016-12-22 エーファウ・グループ・エー・タルナー・ゲーエムベーハー 基板をボンディングする装置および方法
US9899223B2 (en) 2013-09-25 2018-02-20 Ev Group E. Thallner Gmbh Apparatus and method for bonding substrates including changing a stoichiometry of oxide layers formed on the substrates
US10438798B2 (en) 2013-09-25 2019-10-08 Ev Group E. Thallner Gmbh Apparatus and method for bonding substrates
US11139170B2 (en) 2013-09-25 2021-10-05 Ev Group E. Thallner Gmbh Apparatus and method for bonding substrates
JP2020057810A (ja) * 2019-12-23 2020-04-09 エーファウ・グループ・エー・タルナー・ゲーエムベーハー 基板をボンディングする装置および方法
JP2023002767A (ja) * 2019-12-23 2023-01-10 エーファウ・グループ・エー・タルナー・ゲーエムベーハー 基板をボンディングする装置および方法

Also Published As

Publication number Publication date
KR20100114884A (ko) 2010-10-26
EP2091074A1 (en) 2009-08-19
US20110053342A1 (en) 2011-03-03
CN101952934A (zh) 2011-01-19
US8062957B2 (en) 2011-11-22
EP2091070A1 (en) 2009-08-19
WO2009101494A1 (en) 2009-08-20

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