JP2011508451A5 - - Google Patents
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- Publication number
- JP2011508451A5 JP2011508451A5 JP2010540740A JP2010540740A JP2011508451A5 JP 2011508451 A5 JP2011508451 A5 JP 2011508451A5 JP 2010540740 A JP2010540740 A JP 2010540740A JP 2010540740 A JP2010540740 A JP 2010540740A JP 2011508451 A5 JP2011508451 A5 JP 2011508451A5
- Authority
- JP
- Japan
- Prior art keywords
- forming
- opening
- plating
- contact
- peg
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000007747 plating Methods 0.000 claims 22
- 239000004065 semiconductor Substances 0.000 claims 12
- 229920002120 photoresistant polymer Polymers 0.000 claims 9
- 238000000034 method Methods 0.000 claims 8
- 239000002184 metal Substances 0.000 claims 5
- 238000007142 ring opening reaction Methods 0.000 claims 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/966,077 US7811932B2 (en) | 2007-12-28 | 2007-12-28 | 3-D semiconductor die structure with containing feature and method |
| US11/966,077 | 2007-12-28 | ||
| PCT/US2008/086174 WO2009085609A2 (en) | 2007-12-28 | 2008-12-10 | 3-d semiconductor die structure with containing feature and method |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011508451A JP2011508451A (ja) | 2011-03-10 |
| JP2011508451A5 true JP2011508451A5 (enExample) | 2012-02-02 |
| JP5234696B2 JP5234696B2 (ja) | 2013-07-10 |
Family
ID=40797182
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010540740A Active JP5234696B2 (ja) | 2007-12-28 | 2008-12-10 | 収容部を有する三次元半導体ダイ構造及び方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US7811932B2 (enExample) |
| EP (1) | EP2232549B1 (enExample) |
| JP (1) | JP5234696B2 (enExample) |
| KR (1) | KR101558194B1 (enExample) |
| CN (1) | CN101911289B (enExample) |
| TW (1) | TWI470746B (enExample) |
| WO (1) | WO2009085609A2 (enExample) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7612443B1 (en) * | 2003-09-04 | 2009-11-03 | University Of Notre Dame Du Lac | Inter-chip communication |
| US8293587B2 (en) | 2007-10-11 | 2012-10-23 | International Business Machines Corporation | Multilayer pillar for reduced stress interconnect and method of making same |
| US8441123B1 (en) * | 2009-08-13 | 2013-05-14 | Amkor Technology, Inc. | Semiconductor device with metal dam and fabricating method |
| EP2398046A1 (en) * | 2010-06-18 | 2011-12-21 | Nxp B.V. | Integrated circuit package with a copper-tin joining layer and manufacturing method thereof |
| DE102010040065B4 (de) * | 2010-08-31 | 2015-07-23 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verspannungsreduktion in einem Chipgehäuse unter Anwendung eines Chip-Gehäuse-Verbindungsschemas bei geringer Temperatur |
| US8907485B2 (en) | 2012-08-24 | 2014-12-09 | Freescale Semiconductor, Inc. | Copper ball bond features and structure |
| US8907488B2 (en) | 2012-12-28 | 2014-12-09 | Broadcom Corporation | Microbump and sacrificial pad pattern |
| WO2016100470A1 (en) * | 2014-12-17 | 2016-06-23 | Alpha Metals, Inc. | Method for die and clip attachment |
| US9713264B2 (en) | 2014-12-18 | 2017-07-18 | Intel Corporation | Zero-misalignment via-pad structures |
| US10076034B2 (en) * | 2016-10-26 | 2018-09-11 | Nanya Technology Corporation | Electronic structure |
| US10475736B2 (en) | 2017-09-28 | 2019-11-12 | Intel Corporation | Via architecture for increased density interface |
| US10217718B1 (en) * | 2017-10-13 | 2019-02-26 | Denselight Semiconductors Pte. Ltd. | Method for wafer-level semiconductor die attachment |
| JP7251951B2 (ja) * | 2018-11-13 | 2023-04-04 | 新光電気工業株式会社 | 半導体装置及び半導体装置の製造方法 |
| US11862593B2 (en) * | 2021-05-07 | 2024-01-02 | Microsoft Technology Licensing, Llc | Electroplated indium bump stacks for cryogenic electronics |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3138343B2 (ja) | 1992-09-30 | 2001-02-26 | 日本電信電話株式会社 | 光モジュールの製造方法 |
| JPH06310565A (ja) * | 1993-04-20 | 1994-11-04 | Fujitsu Ltd | フリップチップボンディング方法 |
| US5767580A (en) * | 1993-04-30 | 1998-06-16 | Lsi Logic Corporation | Systems having shaped, self-aligning micro-bump structures |
| US5903059A (en) * | 1995-11-21 | 1999-05-11 | International Business Machines Corporation | Microconnectors |
| KR19980025889A (ko) | 1996-10-05 | 1998-07-15 | 김광호 | 중합체층이 개재된 반도체 칩과 기판 간의 범프 접속 구조 |
| JP2845847B2 (ja) * | 1996-11-12 | 1999-01-13 | 九州日本電気株式会社 | 半導体集積回路 |
| US6965166B2 (en) | 1999-02-24 | 2005-11-15 | Rohm Co., Ltd. | Semiconductor device of chip-on-chip structure |
| US6586266B1 (en) * | 1999-03-01 | 2003-07-01 | Megic Corporation | High performance sub-system design and assembly |
| US6365967B1 (en) | 1999-05-25 | 2002-04-02 | Micron Technology, Inc. | Interconnect structure |
| US7087458B2 (en) * | 2002-10-30 | 2006-08-08 | Advanpack Solutions Pte. Ltd. | Method for fabricating a flip chip package with pillar bump and no flow underfill |
| EP1734570A4 (en) * | 2004-03-02 | 2008-03-05 | Fuji Electric Holdings | Method for encapsulating an electronic component |
| JP4331053B2 (ja) * | 2004-05-27 | 2009-09-16 | 株式会社東芝 | 半導体記憶装置 |
| US7348210B2 (en) * | 2005-04-27 | 2008-03-25 | International Business Machines Corporation | Post bump passivation for soft error protection |
| US7781886B2 (en) * | 2005-06-14 | 2010-08-24 | John Trezza | Electronic chip contact structure |
| US7135771B1 (en) * | 2005-06-23 | 2006-11-14 | Intel Corporation | Self alignment features for an electronic assembly |
| US7332423B2 (en) * | 2005-06-29 | 2008-02-19 | Intel Corporation | Soldering a die to a substrate |
| KR100722739B1 (ko) | 2005-11-29 | 2007-05-30 | 삼성전기주식회사 | 페이스트 범프를 이용한 코어기판, 다층 인쇄회로기판 및코어기판 제조방법 |
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2007
- 2007-12-28 US US11/966,077 patent/US7811932B2/en active Active
-
2008
- 2008-12-08 TW TW97147705A patent/TWI470746B/zh not_active IP Right Cessation
- 2008-12-10 JP JP2010540740A patent/JP5234696B2/ja active Active
- 2008-12-10 CN CN2008801227000A patent/CN101911289B/zh not_active Expired - Fee Related
- 2008-12-10 WO PCT/US2008/086174 patent/WO2009085609A2/en not_active Ceased
- 2008-12-10 EP EP08867823.0A patent/EP2232549B1/en not_active Not-in-force
- 2008-12-10 KR KR1020107013959A patent/KR101558194B1/ko not_active Expired - Fee Related
-
2010
- 2010-09-08 US US12/877,193 patent/US8581383B2/en active Active