TWI470746B - 具有圍阻特徵之三維半導體晶粒結構及方法 - Google Patents

具有圍阻特徵之三維半導體晶粒結構及方法 Download PDF

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TWI470746B
TWI470746B TW97147705A TW97147705A TWI470746B TW I470746 B TWI470746 B TW I470746B TW 97147705 A TW97147705 A TW 97147705A TW 97147705 A TW97147705 A TW 97147705A TW I470746 B TWI470746 B TW I470746B
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die
opening
forming
plating
contact
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TW97147705A
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TW200939413A (en
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Scott K Pozder
Ritwik Chatterjee
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Freescale Semiconductor Inc
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Description

具有圍阻特徵之三維半導體晶粒結構及方法
此揭示內容一般係關於半導體器件，且更明確而言係關於具有圍阻特徵之三維半導體晶粒結構及方法。
當形成金屬對金屬、晶粒對晶粒互連時，將放置錯準考量在內，將每一晶粒之對應墊尺寸設為夠大而足以相互覆蓋。對於相等大小的大尺寸墊，接合金屬(諸如錫(Sn))會配設於晶粒之表面上，從而導致不應短路的相鄰互連發生不必要的短路。
存在在將晶粒拾取並放置至一晶圓上之後以及在晶圓層級同時接合晶粒期間晶粒移動的一問題。該晶粒移動可引起在熱壓縮晶粒至晶圓接合期間連接至連接短路或開口錯準。
據此，需要一種用於克服此項技術中上述問題的改良方法及裝置。
本揭示內容之具體實施例有利地提供一種用於滿足及/或超過放置後對齊要求以獲得晶圓級之高產量晶粒接合之方法及裝置。若沒有本揭示內容之具體實施例，在使用諸如環氧樹脂、蠟之黏著劑或具有及不具有熔劑的其他有機黏著劑用於暫時晶粒附著直至接合時，晶粒可能在晶圓上不合需要地偏移。然而，本揭示內容之具體實施例克服在晶圓上的暫時晶粒附著直至接合的此類不合需要偏移。
依據一具體實施例，該方法及裝置包括一樁(45)與一圍阻特徵(62)，其有利地允許在一放置及接合程序期間有機黏著劑從一其中該椿著陸的空間中流出，如本文中所論述。依據本揭示內容之具體實施例之方法包括在一晶粒及晶圓上形成一不對稱大小電鍍椿或墊，使得該等互相嚙合的特徵面積上小於形成該等晶粒至晶圓連接之著陸特徵。在一具體實施例中，最初不接觸的交錯Cu椿及墊結構在使用或不使用熔劑之暫時黏著劑(諸如蠟或環氧樹脂)用以在接合之前保持晶粒時有利地用作晶粒偏移的停止件。而且，該Cu椿及圍阻特徵用以在熱壓縮接合程序期間停止晶粒偏移。該等具體實施例提供程序堅固性及改良晶粒至晶圓對齊。而且，本揭示內容之具體實施例可用於堆疊的晶粒上晶粒、晶圓上晶粒及晶圓上晶圓零件。
現參考圖示，圖1至5係在製造具有依據本揭示內容之一具體實施例之圍阻特徵之一三維半導體晶粒結構中在各種步驟期間一第一晶粒10之一部分之剖面圖。在圖1中，第一晶粒10包括具有主動器件及互連的一半導體晶粒結構12之一部分。半導體晶粒12可包括具有主動器件的任一半導體晶粒。一導電或主動接觸墊14藉由金屬化通道16來耦合至下伏互連及/或主動器件。接觸墊14包含用於半導體晶粒12的一外部接點並可包括任一適當金屬。在一具體實施例中，接觸墊14包含Cu。一鈍化層18位於半導體晶粒12之一層間介電質(ILD)層之一頂部表面上面，其包括位於接觸墊14之一部分上面，同時使接觸墊14之另一部分曝露。鈍化層18包含任一適當鈍化層，其具有約0.25μm至2.0μm的一厚度。例如，鈍化層18可包含藉由適當方法所形成的SiOx、SiN、SiON、有機膜或其組合之一或多個。
一晶種層20係形成於鈍化層18之一頂部表面與接觸墊14之曝露部分上面。在一具體實施例中，晶種層20包括一阻障層部分與一晶種層部分。該阻障層部分係在該晶種層部分之前沈積。例如，晶種層20可包含具有一阻障部分的一Cu晶種層部分，其中該阻障層部分可包括TiW、TiN、W或其他適當阻障材料。該阻障材料防止一上覆金屬在不必要的擴散下往回擴散至接觸墊14內。晶種層20之阻障層部分可包括約0.1至1.0μm的一厚度，而晶種層20之晶種層部分可包括約0.1至1.0μm的一厚度，以獲得約0.2至2.0μm之間的晶種層20之一總厚度。晶種層20可使用任一適當技術(例如物理氣相沈積(PVD)或化學氣相沈積(CVD))來形成。
仍參考圖1，一圖案化光阻22係形成於晶種層20之一頂部表面上面。圖案化光阻22包括一第一開口24，其位於先前藉由鈍化層18內的一開口所曝露的接觸墊14之部分上方，晶種層20位於先前曝露的接觸墊14上面。圖案化光阻22包括一第二開口26，其位於晶種層20之另一部分上面，其中該第二開口具有一剖面尺寸，其小於該第一開口之一對應剖面尺寸。圖案化光阻22包含為習知微影技術所形成的任一適當光阻並可包括約大致13至25μm的一厚度或在比仍待形成的一電鍍接點及電鍍椿特徵厚約至少一微米(1μm)的一厚度。
現參考圖2，使用適當電鍍技術將一金屬沈積至圖1之開口24及26內以形成具有升高邊角部分30的電鍍接點特徵28，以及電鍍椿特徵32。電鍍接點特徵28之升高邊角部分30可由於在位於接觸墊14上面之晶種層20與鈍化層18之邊角邊緣上進行電鍍而發生。在一具體實施例中，電鍍接點特徵28包括一適當二維形狀的一微墊，其係一典型覆晶尺寸之一小部分。該電鍍金屬包含用於一給定晶粒裝配件應用的任一適當金屬，例如Cu。適當電鍍技術可包括在此項技術中所習知的任一適當電鍍或無電極電鍍技術。
在一具體實施例中，電鍍接觸墊28包括約15與54μm之間的一寬度尺寸。此外，電鍍接觸墊28包括一高度尺寸，其在位於鈍化層18上面的晶種層20上方延伸由參考數字29所解說的一量，例如約5.0μm。此外，電鍍接觸墊28之厚度應足以相對於在電鍍接觸墊28(例如，Cu)之頂部上形成一金屬間化合物(例如，Cu3 Sn)消耗一上覆金屬(例如，Sn)，如本文中下面進一步論述。類似地，在一具體實施例中，電鍍椿特徵32包括約4與13μm之間的一寬度尺寸。此外，電鍍椿特徵32具有一高度尺寸，其在位於鈍化層18上面的晶種層20上方延伸由參考數字33所解說的一量，例如約5.5μm。一般情況下，期望高度33在比高度29大約大致0.5μm。而且，電鍍接點特徵28之面積與電鍍椿特徵32之面積的比率係約2.75:1至36:1。
現參考圖3，使用適當技術在電鍍接點特徵(或微墊)28與電鍍椿特徵32之頂部表面上面沈積用於形成一金屬間化合物的一金屬。位於電鍍接點特徵28上面的金屬係由參考數字34來加以指示而位於電鍍椿特徵32上面的金屬係由參考數字36來加以指示。在一具體實施例中，金屬34及36包含Sn。額外金屬可包括銦、金、銀、銀銅合金、鉛錫、焊料金屬或其組合，其依據一給定晶粒裝配件應用之要求來選擇。用於沈積金屬34及36的適當技術可包括此項技術中所習知的任一適當電解電鍍或浸沒式電鍍程序。
在形成金屬34及36之後，使用適當技術移除圖案化光阻22，例如使用一適當濕式剝除或乾式蝕刻。移除圖案化光阻22曝露晶種層20之若干部分，包括在電鍍接觸墊28及電鍍椿特徵32外區域內的晶種層部分及其阻障層部分。在移除圖案化光阻22之後，使用一適當蝕刻或剝除來移除晶種層20之曝露部分，其中輕度氧化由晶種層移除所曝露的電鍍接觸墊28與電鍍椿特徵32之側壁。如圖4中所示，晶種層20仍在電鍍接觸墊28與電鍍椿特徵32底下。此外，移除晶種層20導致電鍍接點特徵28與電鍍椿特徵32之一些底切，其中分別在電鍍接點特徵28與電鍍椿特徵32之上部周邊周圍並分別在對應金屬層34及36下面產生外伸區域38及40。換言之，外伸區域38及40分別對應於金屬34及36之懸臂部分。
在一具體實施例中，金屬層34及36之外伸區域38及40分別使下伏電鍍金屬外伸約大致1μm的一量。此外，在移除晶種層20之曝露部分之程序期間在寬度上減少電鍍椿特徵32。在一具體實施例中，電鍍椿特徵32係減少約2.0與12μm之間的一寬度尺寸。
現參考圖5，圖4之結構經歷一快速熱退火，其足以分別將金屬34及36回焊至回焊金屬42及44內。該退火係足以在電鍍接觸墊28與細薄化椿特徵32上引起該金屬之一所需回焊，並最低限度地形成金屬間化合物。由於電鍍接觸墊28之更大寬度尺寸及所需回焊，在該特徵之頂部上面的金屬34在該退火期間變形成一一般弧形形狀42。由於變細椿特徵32之更細寬度尺寸及所需回焊，在該特徵之頂部上面的金屬36在該退火期間變形成一一般球形形狀44。減少寬度的椿特徵32與回焊的球形上覆金屬44一起形成一椿45，用於限制晶粒裝配件10相對於晶粒裝配件50之一移動，如本文中下面參考圖7及8進一步論述。
依據一具體實施例，一般球形形狀44係特徵化為約最小4μm2 至最大144μm2 之間的一剖面面積。此外，電鍍接觸墊28與回焊金屬42包括一高度尺寸，其在鈍化層18上方延伸由參考數字46所解說的一量，例如約8.0μm。類似地，在一具體實施例中，電鍍椿特徵32與回焊金屬球形44一起具有一高度尺寸，其在鈍化層18上方延伸由參考數字48所解說的一量，例如約10.5μm。一般情況下，期望高度48在比高度46大約大致2.0至2.5μm。
圖6係在製造具有依據本揭示內容之一具體實施例之圍阻特徵之一三維半導體晶粒結構中在另一步驟期間一第二晶粒裝配件50之一部分之一剖面圖。在圖6中，第二晶粒裝配件50包括類似特徵並以與圖5之第一半導體晶粒部分類似之一方式來形成，差異如本文中所述。第二晶粒裝配件50包括一半導體晶粒52。半導體晶粒52可包括具有主動器件的任一半導體晶粒。一導電或主動接觸墊54藉由金屬化通道56來耦合至下伏互連及/或主動器件。接觸墊54包含用於半導體晶粒部分52的一外部接點並可包括任一適當金屬。在一具體實施例中，接觸墊54包含Cu。一鈍化層58位於半導體晶粒52之一層間介電質(ILD)層之一頂部表面上面，其包括位於接觸墊54之一部分上，同時使接觸墊54之另一部分曝露。鈍化層58包含任一適當鈍化層，其具有約0.25μm至2.0μm的一厚度。例如，鈍化層58可包含藉由適當方法所形成的SiOx、SiN、SiON、有機膜或其組合之一或多個。
一晶種層60係形成於鈍化層58之一頂部表面與接觸墊54之曝露部分上面。在一具體實施例中，晶種層60包括一阻障層部分與一晶種層部分。該阻障層部分係在該晶種層部分之前沈積。例如，晶種層60可包含具有一阻障部分的一Cu晶種層部分，其中該阻障層部分可包括TiW、TiN、W或其他適當阻障材料。該阻障材料防止一上覆金屬之不合需要擴散擴散回至接觸墊54內。晶種層60之阻障層部分可包括約0.1至1.0μm的一厚度而晶種層60之晶種層部分可包括約0.1至1.0μm的一厚度以獲得約0.2至2.0μm的晶種層60之一總厚度。晶種層60可使用任一適當技術(例如物理氣相沈積(PVD)或化學氣相沈積(CVD))來形成。
仍參考圖6，包含該圍阻特徵之元件64及66的一圍阻特徵62以及電鍍接觸墊(或微墊)68係以一類似於圖2至4之電鍍椿特徵32及電鍍接觸墊(或微墊)28的方式來形成。特定言之，使用適當電鍍技術將一金屬沈積至一圖案化光阻(未顯示)之對應開口內，以形成具有升高邊角部分的電鍍接點特徵68以及圍阻特徵62之電鍍特徵元件64及66。圍阻特徵62之電鍍特徵元件64及66彼此分離一量，如本文中下面將結合圖10及11所解釋。微墊68與圍阻特徵62之電鍍金屬包含用於一給定晶粒裝配件應用的任一適當金屬，例如Cu。適當電鍍技術可包括在此項技術中所習知的任一適當電鍍或無電鍍技術。
在一具體實施例中，電鍍接觸墊68包括約15與54μm之間的一寬度尺寸。此外，電鍍接觸墊68包括一高度尺寸，其在位於鈍化層58上面的晶種層60上方延伸一量，例如約5.0μm。此外，電鍍接觸墊68之厚度應足以相對於相鄰電鍍接觸墊68(例如，Cu)之頂部形成一金屬間化合物(例如，Cu3 Sn)消耗一上覆金屬(例如，Sn)，如本文中下面進一步論述。類似地，在一具體實施例中，圍阻特徵62之特徵元件64及66包括約4與13μm之間的一寬度尺寸。此外，圍阻特徵62之特徵元件64及66具有一高度尺寸，其在位於鈍化層58上面的晶種層60上方延伸約5.5μm的一量。一般情況下，期望相對於圍阻特徵62之特徵元件64及66的高度比電鍍接點特徵或微墊68的高度大約大致0.5μm。而且，電鍍接點特徵68之面積與圍阻特徵62之圍阻特徵元件64及66之至少一者之面積的比率係約2.75:1至36:1。
圖7係在製造具有依據本揭示內容之一具體實施例之圍阻特徵62之一三維半導體晶粒結構中在另一步驟期間第一晶粒裝配件10相對於一第二晶粒裝配件50之放置之一剖面圖。特定言之，一預定義量的適當材料70係散佈於晶粒裝配件50之一表面上的一給定位置內，且在晶粒裝配件50之上放置晶粒裝配件10之際，將材料70分佈於該兩個晶粒裝配件之間。分佈材料70可(例如)由於在該兩個晶粒裝配件之間材料之毛細管作用、在該等晶粒裝配件之間的材料壓縮或其他方式而發生。材料70可包含(例如)一適當蠟材料，或一或多個有機黏著劑，諸如一環氧樹脂。材料70還可能包含空氣。在一後續處理步驟中，可經由適當技術(諸如蒸發)來移除材料70，如本文中下面結合圖10及11之論述將會更清楚地明白。
在晶粒裝配件50之上放置晶粒裝配件10包括在微墊68上佈置微墊28。此外，椿45係位於圍阻特徵62之元件64與66之間的區域內。給定在對應鈍化層18上方椿45之高度係大於微墊28與回焊金屬42之一組合高度，且給定圍阻特徵62之元件64與66之高度係大於微墊68之一高度，則在晶粒裝配件50之上放置晶粒裝配件10之際，椿45之頂端在圍阻特徵62之元件64及66之頂端下面延伸，例如如圖7中所解說。由此，在第二晶粒裝配件50之上放置第一晶粒裝配件10之後，第一晶粒裝配件10在其相對於第二晶粒裝配件50橫向移動的能力上受到限制。
特定言之，要是第一晶粒裝配件10移動至圖7之右手側，其移動將會在椿45實體接觸圍阻特徵62之元件66時受到限制。此外，要是第一晶粒裝配件10移動至圖7之左手側，其移動將會在椿45實體接觸圍阻特徵62之元件64時受到限制。此外，一晶粒裝配件相對於另一者之移動係由於在該兩個晶粒裝配件之間存在材料70而受到液壓阻尼。
圖8係在製造具有依據本揭示內容之一具體實施例之圍阻特徵62之一三維半導體晶粒結構76中在另一步驟期間第一晶粒裝配件10與一第二晶粒裝配件50之熱壓縮接合之一剖面圖。在第二晶粒裝配件50之上放置第一晶粒裝配件10之後，使用在此項技術中習知用於熱壓縮接合之適當設備及處理，經由熱壓縮接合來處理該組合結構。一般地，用於在第二晶粒裝配件50之上放置第一晶粒裝配件10之位置發生於一實體位置內，該實體位置不同於該熱壓縮接合之位置。在從放置站移動至熱壓縮接合站期間，放置的第一晶粒裝配件10可能已相對於第二晶粒裝配件50橫向移動；然而，此橫向移動由於在第二晶粒裝配件50之圍阻特徵62內存在第一晶粒裝配件10之椿45而受到限制。
在熱壓縮接合期間，將第一晶粒裝配件10在第二晶粒裝配件50上壓縮一量，其係足以移動有機材料70並允許一所需接合發生。例如，在一具體實施例中，該接合壓力係約4.5psi至27psi。在另一具體實施例中，該接合力對於一200mm晶圓包含約1000至6000牛頓。此外，熱壓縮接合之熱部分包括在處理期間升高溫度至一足以形成金屬間化合物的所需位準。在一具體實施例中，該接合金屬包含Sn，而對應電鍍墊(或微墊)包含Cu。在此一實例中，用於熱壓縮接合的溫度包括大於232℃以熔化Sn並形成Cu3 Sn與Cu6 Sn5 金屬間化合物。
換言之，熱壓縮引起在第一晶粒裝配件10之回焊金屬42及微墊28與圖7之第二晶粒裝配件50之微墊68之間形成金屬間化合物，並特定言之形成圖8之金屬間化合物接合72。圖8還解說第一晶粒裝配件10已相對於第二晶粒裝配件50橫向移動之一範例，其中該移動由於椿45接觸圍阻特徵62之元件66而受到限制。由此，此外，該熱壓縮引起在椿45之變細椿特徵32上的回焊金屬44在第一晶粒裝配件10之回焊金屬44及變細椿特徵32與圖7之第二晶粒裝配件50之元件66之間形成金屬間化合物，且特定言之形成圖8之金屬間化合物74。形成金屬間化合物72及74導致消耗第一晶粒裝配件10與第二晶粒裝配件50之對應特徵之金屬。
圖9係在製造具有依據本揭示內容之一具體實施例之圍阻特徵之一三維半導體晶粒結構中所使用之第一晶粒部分10與第二晶粒部分50之鄰接面的一俯視圖。特定言之，第一晶粒部分10與第二晶粒部分50之鄰接互補面係解說為分開，如參考數字77進一步指示。第一晶粒部分10之面包括微墊28及82(未顯示一上面回焊金屬)與椿45及78，其中如先前所論述，微墊82及椿78分別類似於微墊28(具有上面回焊金屬)與椿45。圖5中所解說之剖面係沿在圖9之第一晶粒部分10上的線5-5所截取。第二晶粒部分50之面包括微墊68及84與圍阻特徵62及80，其中如先前所論述，微墊84與圍阻特徵80分別類似於微墊68與圍阻特徵62。圖6中所解說之剖面係沿在圖9之第二晶粒部分50上的線6-6所截取。當鄰接面放置於另一者頂部時，微墊28(圖9中未顯示回焊金屬42)位於微墊68上面，微墊82(圖9中未顯示一回焊金屬)位於微墊84上面，椿45係佈置於圍阻特徵62內，而椿78係佈置於圍阻特徵80內。由於在該等第一及第二晶粒裝配件之間具有椿及圍阻特徵，該第一晶粒部分相對於該第二晶粒部分之放置及任何後續移動均使用(例如)如邊界86所定義的一區域內來圍阻。
圖10及11係用於具有依據本揭示內容之一具體實施例之圍阻特徵之一三維半導體晶粒結構中第一晶粒部分10之一椿特徵45與第二晶粒部分50之一圍阻特徵62之更詳細圖式表示。特定言之，圖10提供椿45之一俯視圖，其包含一變細椿特徵32(為了方便解說，未顯示一上面回焊金屬44)。圖10進一步提供圍阻特徵62之一俯視圖。如本文中更早所論述，圍阻特徵62包含元件64及66。圍阻特徵62包括其他元件88、90、92、94、96及98，其在性質上與元件64及66類似。圖10之圖解進一步顯示在椿45與圍阻特徵62之環繞元件之間的一所需間隔。特定言之，當在圍阻特徵62之該等元件之間大致對中時，椿45與該圍阻特徵間隔一量，其約在將晶粒部分圍阻椿45拾取並放置於圍阻特徵64、66、88、90、92、94、96及98的晶粒部分上時晶粒部分圍阻椿45之放置未對齊，如箭頭100及102所表示。圖7中所解說之剖面之一部分(包括椿45與元件64及66)係沿圖10之線7-7所截取。
仍參考圖10，元件64、88、90、66、92、94、96及98與其相鄰者隔開一量，該量足以讓有機黏著劑材料之進入及逸出，但不足以使椿45在其相鄰者之間穿過。據此，椿45係限制於圍阻特徵62之元件64、88、90、66、92、94、96及98所定義之一圍阻區域99內移動。黏滯材料之進入可從在該圍阻特徵之兩個相鄰元件之上及/或之間的任一方向發生，諸如由參考數字104所指示。而且，黏滯材料之逸出可在不遇到黏滯材料進入的任一方向上發生，例如如參考數字106及108所指示。該黏滯材料相當於有機黏著材料70，如本文中先前所論述。
圖11提供椿45及圍阻特徵62之一俯視圖，其類似於圖10中所解說者，但具有下列差異。在圖11中，椿45已相對於圍阻特徵62偏移或移動。特定言之，椿45已移動至圍阻特徵62之右手側，但由於存在元件66及92而防止其進一步移動至右邊。如上所論述，在該圍阻特徵之相鄰元件之間的間隔係足以使有機黏著材料進入及逸出，但不足以允許椿45移動至該圍阻特徵之邊界99外。黏滯材料之進入可從在該圍阻特徵之兩個相鄰元件之上及/或之間的任一方向發生，諸如由參考數字104所指示。而且，黏滯材料之出去可在不遭遇黏滯材料進入的任一方向上發生，例如如參考數字108及110所指示。在圖11中，圖10之先前的逸出106由於相鄰元件66及92之間有椿45存在而受到阻隔。而且，圖8中所解說之剖面之一部分(包括椿45與元件64及66)係沿圖11之線8-8所截取。
圍阻特徵62之元件64、88、90、66、92、94、96及98之數目及組態可以不同於該圖示中所解說的該等者。如本文中所揭示，可依據具有一圍阻特徵的一給定三維半導體晶粒結構的要求來選擇特定尺寸、組態或配置及相鄰元件之間的空隙。此外，一第一晶粒部分之椿及微墊與一第二晶粒部分之圍阻特徵及微墊在所得三維半導體晶粒結構中形成該第一晶粒部分與該第二晶粒部分之互補特徵。
本文所說明之半導體基板可以係任何半導體材料或材料組合，諸如砷化鎵、矽鍺、絕緣物上矽(SOI)、矽、單晶矽等及以上之組合。
至此，應瞭解，已提供一種晶粒上晶粒裝配件，其包含：一第一晶粒，其具有一第一接點延伸部並具有一樁，該椿在該第一晶粒上方延伸一第一高度；及一第二晶粒，其具有連接至該第一接點延伸部的一第二接點延伸部並具有在該第二晶粒上方延伸一第二高度的一圍阻特徵，其環繞該椿，其中該椿延伸越過該圍阻特徵。該椿可包含相鄰於該第一晶粒的一第一金屬與在該椿之遠離該第一晶粒之一末端上的一第二金屬。在一具體實施例中，該第二金屬包含錫，其中該第一高度係大於該第二高度。在另一具體實施例中，在與該第二金屬之一界面處該第一金屬之一面積係小於144平方微米。依據另一具體實施例，該第一高度與該第二高度之一和超過該第一接點延伸部之一高度與該第二接點延伸部之一高度的一和。
在一另外具體實施例中，該圍阻特徵包含從該第二晶粒延伸的複數個元件，其定義一移動約束區域，其中該椿係在該移動約束區域內。在又一另外具體實施例中，該圍阻特徵係用於限制該第二晶粒相對於該第一晶粒之移動，使得該第一外部接點在一預定容限內對齊該第二外部接點。在又一另外具體實施例中，該第一晶粒係進一步特徵化為具有一第二椿；且該第二椿係進一步特徵化為具有在該第二晶粒上方延伸該第二高度的一第二圍阻區域，其環繞該第二椿。
依據另一具體實施例，一種形成一晶粒上晶粒裝配件之方法，其包含在一第一半導體晶粒上形成一第一外部接點；在該第一半導體晶粒之上，包括在該第一外部按點之上，形成一第一晶種層；在該第一晶種層之上形成一第一光阻層，其具有一第一開口與一第二開口，其中該第一開口係在該第一外部接點之上；執行一電鍍步驟以在該第一開口內形成一第一電鍍接點，並在該第二開口內形成一樁；移除該第一光阻層；及在相鄰於該第一電鍍接點及該椿的區域內移除該第一晶種層。該方法進一步包含在一第二半導體晶粒上形成一第二外部接點；在該第二半導體晶粒之上且包括在該第二外部接點之上形成一第二晶種層；在該第二晶種層之上形成一第二光阻層，其具有一第三開口與一環狀開口，其中該第三開口係在該第二外部接點之上；執行一電鍍步驟以在該第三開口內形成一第二電鍍接點，並在用於定義一圍阻區域的該環狀開口內形成一圍阻特徵，該圍阻區域係用於限制在該第一半導體晶粒與該第二半導體晶粒之間的移動；移除該第二光阻層；及在相鄰於該第二電鍍接點與該圍阻特徵的區域內移除該第二晶種層。該方法又進一步包含使該第一半導體晶粒接觸該第二半導體晶粒而放置，使得該第一電鍍接點係接觸該第二電鍍接點且該椿係在該圍阻區域內。
在另一具體實施例中，執行一電鍍步驟以在該第一開口內形成該第一電鍍接點並在該第二開口內形成該椿的該步驟係進一步特徵化為形成該椿至一高度，其大於該第一電鍍接點之一高度。此外，執行一電鍍步驟以在該第一開口內形成該第一電鍍接點並在該第二開口內形成該椿的該步驟係進一步特徵化為在該第一開口內形成一第一電鍍部分，在該第二開口內形成一第一椿部分，在該第一電鍍部分上形成一第一金屬層，並在該第一椿部分上形成一第二金屬層。而且，執行一電鍍步驟以在該第一開口內形成該第一電鍍接點並在該第二開口內形成該椿的該步驟係進一步特徵化為該第一金屬層與該第二金屬層包含錫。而且，形成該第一光阻層的該步驟係進一步特徵化為該第一開口具有大於該第二開口之一面積的一面積。又另外，移除該晶種層之該步驟係進一步特徵減少該椿之寬度，使得該第一椿部分之一頂部表面具有不大於144平方微米的一面積。
依據一另外具體實施例，形成該第二光阻層的該步驟係進一步特徵化為該環狀開口包含在該第二光阻層內的複數個開口，其以一閉環配置。執行該電鍍步驟以在該第三開口內形成一第二電鍍接點並在該環狀開口內形成一圍阻特徵的該步驟係進一步特徵化為該圍阻特徵係形成於該複數個開口內使得該圍阻特徵包含以閉環配置的複數個金屬元件。
依據另一具體實施例，該方法進一步包括：在該第一晶種層之上形成一第一光阻層的該步驟進一步特徵化為該第一光阻層具有一第五開口；執行一電鍍步驟以在該第一開口內形成一第一電鍍接點並在該第二開口內形成一椿的該步驟進一步特徵化為在該第五開口內形成一第二椿；在相鄰於該第一電鍍接點與該椿之區域內移除該第一晶種層的該步驟亦移除相鄰於該第二椿的該第一晶種層；在該第二晶種層之上形成該第二光阻層的該步驟進一步特徵化為該第二光阻層具有一第二環狀開口；執行一電鍍步驟以在該第三開口內形成一第二電鍍接點並在該環狀開口內形成一圍阻特徵之該步驟進一步特徵化在該第二環狀開口內形成用於定義一第二圍阻區域的一第二圍阻特徵，該第二圍阻區域係用於約束在該第一半導體晶粒與該第二半導體晶粒之間的移動；在相鄰於該第二電鍍接點與該圍阻特徵之區域內移除該第二晶種層的該步驟進一步特徵化為移除相鄰於該第二圍阻特徵的該第二晶種層；且使該第一半導體晶粒接觸該第二半導體晶粒的該步驟進一步特徵化該第二椿係在該第二圍阻區域內。
依據另一具體實施例，一種形成一晶粒上晶粒裝配件之方法，其包含：在一第一半導體晶粒上形成一第一接點延伸部，其從該第一半導體晶粒延伸，並在該第一半導體晶粒上形成一第一椿與一第二椿；在一第二半導體晶粒上形成一第二接點延伸部並形成環繞一第一圍阻區域的一第一圍阻特徵與環繞一第二圍阻區域的一第二圍阻特徵；使該第一接點延伸部接觸該第二接點延伸部而放置，該第一椿在該第一圍阻區域內，且該第二椿在該第二圍阻區域內；以及將該第一接點延伸部與該第二接點延伸部熱壓縮接合在一起，同時藉由該第一圍阻區域內之該第一椿及該第二圍阻區域內之該第二椿，將該等第一及第二接點延伸部之橫向移動約束至一預定量。在一另外具體實施例中，形成該第一接點延伸部之該等步驟與形成該第二接點延伸部之該等步驟之至少一者係進一步特徵化為執行錫的一沈積及退火，其中該第一接點延伸部之一高度與該第二接點延伸部之一高度的一和係小於該第一椿之一高度與該第一圍阻區域之一高度的一和。
因為用於實施本發明的裝置大部分係由習知此項技術者所已知的組件組成，故為了明白並理解本發明的基本概念且為了不混淆或偏離本發明之教示內容，將不會在比以上說明認為必要者更大的程度上解釋特定細節。
而且，本說明書及申請專利範圍中"前"、"後"、"頂部"、"底部"、"之上"、"底下"等術語(若存在的話)係用於說明目的且不一定用於說明永久性相對位置。應明白，在適當情形下，可互換所使用的該等術語，使得本文所說明的本發明之具體實施例(例如)能夠以本文所解說或另外說明之方位以外的方位操作。
儘管本文中參考特定具體實施例來說明本發明，但是可進行各種修改及變更而不脫離以下專利申請範圍所提出之本發明之範疇。例如，該第一晶粒可能包含兩個椿及圍阻特徵，其中該第二晶粒包含圍阻特徵及椿之互補對應者。此外，本揭示內容之具體實施例可相對於用於現在或未來的任一技術世代上的三維整合來實施。據此，應在一解說性而非一限制性意義上考量本說明書及圖式，並且期望所有此類修改均涵蓋在本發明之範疇內。不期望將本文關於特定具體實施例所說明之任何好處、優點或問題解決方案視為任一或所有請求項之一關鍵，必要或本質特徵或要素。
本文所使用的術語"耦合"並不意在侷限於一直接耦合或一機械耦合。
而且，本文中所使用的術語"一"或"一個"係定義為一或一個以上。而且，在申請專利範圍中使用諸如"至少一"及"一或多個"之介紹性短語不應視為暗示著藉由不定冠詞"一"或"一個"介紹另一請求項元件會將包含此類介紹請求項元件之任一特定請求項限制於僅包含一此類元件之發明，即使相同請求項包括介紹性短語"一或多個"或"至少一"及諸如"一"或"一個"之不定冠詞。此亦適用於定冠詞之用法。
除非另有聲明，諸如"第一"及"第二"之術語係用來任意區分此類術語所說明的元件。因而，該些術語不一定意在指示此類元件之時間或其他優先性。
10．．．第一晶粒/第一晶粒裝配件/第一晶粒部分
12．．．半導體晶粒結構/半導體晶粒
14．．．導電或主動接觸墊
16．．．金屬化通道
18．．．鈍化層
20．．．晶種層
22．．．圖案化光阻
24．．．第一開口
26．．．第二開口
28．．．第一接點延伸部/電鍍接點特徵/電鍍接觸墊/微墊
29．．．高度
30．．．升高邊角部分
32．．．椿/電鍍椿特徵
33．．．高度
34．．．金屬/金屬層
36．．．金屬/金屬層
38．．．外伸區域
40．．．外伸區域
42．．．第一接點延伸部/回焊金屬/大致弧形形狀
44．．．椿/回焊金屬/大致球形形狀/回焊金屬球形
45．．．椿/樁特徵
46．．．高度
48．．．高度
50．．．第二晶粒/第二晶粒裝配件/第二晶粒部分
52．．．半導體晶粒
54．．．導電或主動接觸墊
56．．．金屬化通道
58．．．鈍化層
60．．．晶種層
62．．．圍阻特徵
64．．．電鍍特徵元件/圍阻特徵
66．．．電鍍特徵元件/圍阻特徵
68．．．第二接點延伸部/電鍍接點特徵/微墊
70．．．材料/有機黏著材料
72．．．金屬間化合物接合/金屬化合物
74．．．金屬間化合物
76．．．三維半導體晶粒結構
78．．．椿
80．．．圍阻特徵
82．．．微墊
84．．．微墊
86．．．邊界
88．．．元件/圍阻特徵
90．．．元件/圍阻特徵
92．．．元件/圍阻特徵
94．．．元件/圍阻特徵
96．．．元件/圍阻特徵
98．．．元件/圍阻特徵
99．．．圍阻區域/邊界
本發明已藉由範例予以說明且不受附圖限制，其中相同參考符號指示類似元件。在該等圖示中的元件係出於簡化及清楚而解說且不一定依比例繪製。
圖1至5係在製造具有依據本揭示內容之一具體實施例之圍阻特徵之一三維半導體晶粒結構中在各種步驟期間一第一晶粒裝配件之一部分之一剖面圖；
圖6係在製造具有依據本揭示內容之一具體實施例之圍阻特徵之一三維半導體晶粒結構中在另一步驟期間一第二晶粒裝配件之一部分之一剖面圖；
圖7係在製造具有依據本揭示內容之一具體實施例之圍阻特徵之一三維半導體晶粒結構中在另一步驟期間該第一晶粒裝配件之部分相對於該第二晶粒裝配件之部分之放置之一剖面圖；
圖8係在製造具有依據本揭示內容之一具體實施例之圍阻特徵之一三維半導體晶粒結構中在另一步驟期間該第一晶粒裝配件之部分與該第二晶粒裝配件之部分之熱壓縮接合之一剖面圖；
圖9係在製造具有依據本揭示內容之一具體實施例之圍阻特徵之一三維半導體晶粒結構中該第一晶粒裝配件之部分與第二晶粒裝配件之部分之鄰接面的一俯視圖；以及
圖10及11係用於具有依據本揭示內容之一具體實施例之圍阻特徵之一三維半導體晶粒結構中該第一晶粒裝配件之一椿特徵與第二晶粒裝配件之一圍阻特徵之更詳細圖式表示。
10．．．第一晶粒/第一晶粒裝配件/第一晶粒部分
12．．．半導體晶粒結構/半導體晶粒
14．．．導電或主動接觸墊
16．．．金屬化通道
18．．．鈍化層
20．．．晶種層
28．．．第一接點延伸部/電鍍接點特徵/電鍍接觸墊/微墊
32．．．椿/電鍍椿特徵
42．．．第一接點延伸部/回焊金屬/大致弧形形狀
44．．．椿/回焊金屬/一般球形形狀/回焊金屬球形
45．．．椿/樁特徵
50．．．第二晶粒/第二晶粒裝配件
52．．．半導體晶粒
54．．．導電或主動接觸墊
56．．．金屬化通道
58．．．鈍化層
60．．．晶種層
62．．．圍阻特徵
64．．．電鍍特徵元件/圍阻特徵
66．．．電鍍特徵元件/圍阻特徵
68．．．第二接點延伸部/電鍍接點特徵/微墊
70．．．材料/有機黏著材料

Claims (17)

  1. 一種晶粒上晶粒裝配件，其包含：一第一晶粒，其具有一第一接點延伸部，並具有在該第一晶粒上方延伸一第一高度的一椿，其中該椿包含相鄰於該第一晶粒的一第一金屬與在該椿之遠離該第一晶粒之一末端上的一第二金屬；以及一第二晶粒，其具有連接至該第一接點延伸部的一第二接點延伸部，並具有在該第二晶粒上方延伸一第二高度的一圍阻特徵，其環繞該椿，其中該椿延伸越過該圍阻特徵。
  2. 如請求項1之晶粒上晶粒裝配件，其中該第二金屬包含錫。
  3. 如請求項2之晶粒上晶粒裝配件，其中該第一高度係大於該第二高度。
  4. 如請求項3之晶粒上晶粒裝配件，其中在與該第二金屬之一界面處該第一金屬之一面積係小於144平方微米。
  5. 如請求項1之晶粒上晶粒裝配件，其中該第一高度與該第二高度的一和超過該第一接點延伸部之一高度與該第二接點延伸部之一高度的一和。
  6. 如請求項1之晶粒上晶粒裝配件，其中該圍阻特徵包含從該第二晶粒延伸的複數個元件，其定義一約束移動區域，其中該椿係在該約束移動區域內。
  7. 如請求項1之晶粒上晶粒裝配件，其中該圍阻特徵係用於限制該第二晶粒相對於該第一晶粒之移動，使得第一 外部接點在一預定容限內對齊第二外部接點。
  8. 如請求項1之晶粒上晶粒裝配件，其中：該第一晶粒係進一步特徵化為具有一第二椿；以及該第二晶粒係進一步特徵化為具有在該第二晶粒上方延伸該第二高度的一第二圍阻區域，其環繞該第二椿。
  9. 一種形成一晶粒上晶粒裝配件之方法，其包含：在一第一半導體晶粒上形成一第一外部接點；在該第一半導體晶粒之上，包括在該第一外部接點之上形成一第一晶種層；在該第一晶種層上形成一第一光阻層，其具有一第一開口與一第二開口，其中該第一開口係在該第一外部接點之上；執行一電鍍步驟以在該第一開口內形成一第一電鍍接點，並在該第二開口內形成一椿；移除該第一光阻層；在相鄰於該第一電鍍接點與該椿之區域內移除該第一晶種層；在一第二半導體晶粒上形成一第二外部接點；在該第二半導體晶粒之上且包括在該第二外部接點之上形成一第二晶種層；在該第二晶種層上形成一第二光阻層，其具有一第三開口與一環狀開口，其中該第三開口係在該第二外部接點之上；執行一電鍍步驟以在該第三開口內形成一第二電鍍接 點，並在用於定義一圍阻區域的該環狀開口內形成一圍阻特徵，該圍阻區域係用於約束在該第一半導體晶粒與該第二半導體晶粒之間的移動；移除該第二光阻層；在相鄰於該第二電鍍接點與該圍阻特徵之區域內移除該第二晶種層；以及使該第一半導體晶粒接觸該第二半導體晶粒而放置，使得該第一電鍍接點係接觸該第二電鍍接點且該椿係在該圍阻區域內。
  10. 如請求項9之方法，其中執行一電鍍步驟以在該第一開口內形成該第一電鍍接點並在該第二開口內形成該椿的該步驟係進一步特徵化為形成該椿至一高度，其大於該第一電鍍接點之一高度。
  11. 如請求項10之方法，其中執行一電鍍步驟以在該第一開口內形成該第一電鍍接點並在該第二開口內形成該椿的該步驟係進一步特徵化為在該第一開口內形成一第一電鍍部分，在該第二開口內形成一第一椿部分，在該第一電鍍部分上形成一第一金屬層，並在該第一椿部分上形成一第二金屬層。
  12. 如請求項11之方法，其中執行一電鍍步驟以在該第一開口內形成該第一電鍍接點並在該第二開口內形成該椿的該步驟係進一步特徵化為該第一金屬層與該第二金屬層包含錫。
  13. 如請求項12之方法，其中形成該第一光阻層的該步驟係 進一步特徵化為該第一開口具有大於該第二開口之一面積的一面積。
  14. 如請求項13之方法，其中移除該晶種層之該步驟係進一步特徵化為減少在該第二金屬層底下的該椿之該部分的一寬度，使得該第一椿部分之一頂部表面具有不大於144平方微米的一面積。
  15. 如請求項9之方法，其中形成該第二光阻層的該步驟係進一步特徵化為該環狀開口包含在該第二光阻層內的複數個開口，其以一閉環配置。
  16. 如請求項15之方法，其中執行該電鍍步驟以引起在該第三開口內形成一第二電鍍接點並在該環狀開口內形成一圍阻特徵的該步驟係進一步特徵化為該圍阻特徵係形成於該複數個開口內使得該圍阻特徵包含以閉環配置的複數個金屬元件。
  17. 如請求項9之方法，其中：在該第一晶種層上形成一第一光阻層之步驟係進一步特徵化為該第一光阻層具有一第五開口；執行一電鍍步驟以在該第一開口內形成一第一電鍍接點並在該第二開口內形成一椿的該步驟係進一步特徵化為在該第五開口內形成一第二椿；在相鄰於該第一電鍍接點與該椿之區域內移除該第一晶種層之該步驟亦移除相鄰於該第二椿的該第一晶種層；在該第二晶種層上形成該第二光阻層之該步驟係進一 步特徵化為該第二光阻層具有一第二環狀開口；執行一電鍍步驟以引起在該第三開口內形成一第二電鍍接點並在該環狀開口內形成一圍阻特徵之該步驟係進一步特徵化為在該第二環狀開口內形成用於定義一第二圍阻區域的一第二圍阻特徵，該第二圍阻區域係用於約束在該第一半導體晶粒與該第二半導體晶粒之間的移動；在相鄰於該第二電鍍接點與該圍阻特徵之區域內移除該第二晶種層之該步驟係進一步特徵化為移除相鄰於該第二圍阻特徵的該第二晶種層；以及使該第一半導體晶粒接觸該第二半導體晶粒之該步驟係進一步特徵化為該第二椿係在該第二圍阻區域內。
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CN101911289A (zh) 2010-12-08
EP2232549A2 (en) 2010-09-29
EP2232549A4 (en) 2011-04-06
TW200939413A (en) 2009-09-16
US8581383B2 (en) 2013-11-12
CN101911289B (zh) 2012-10-03
US7811932B2 (en) 2010-10-12
JP5234696B2 (ja) 2013-07-10
US20090166888A1 (en) 2009-07-02
WO2009085609A2 (en) 2009-07-09
KR20100102132A (ko) 2010-09-20
WO2009085609A3 (en) 2009-09-03
KR101558194B1 (ko) 2015-10-07
US20100327440A1 (en) 2010-12-30
EP2232549B1 (en) 2018-09-19

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