CN101911289B - 具有限制部件的三维半导体管芯结构及其制造方法 - Google Patents

具有限制部件的三维半导体管芯结构及其制造方法 Download PDF

Info

Publication number
CN101911289B
CN101911289B CN2008801227000A CN200880122700A CN101911289B CN 101911289 B CN101911289 B CN 101911289B CN 2008801227000 A CN2008801227000 A CN 2008801227000A CN 200880122700 A CN200880122700 A CN 200880122700A CN 101911289 B CN101911289 B CN 101911289B
Authority
CN
China
Prior art keywords
die
contact
peg
opening
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2008801227000A
Other languages
English (en)
Chinese (zh)
Other versions
CN101911289A (zh
Inventor
S·K·波兹德
R·查特杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN101911289A publication Critical patent/CN101911289A/zh
Application granted granted Critical
Publication of CN101911289B publication Critical patent/CN101911289B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H10W72/01233—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01235—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01255—Changing the shapes of bumps by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01257—Changing the shapes of bumps by reflowing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
    • H10W72/01938—Manufacture or treatment of bond pads using blanket deposition in gaseous form, e.g. by CVD or PVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01951—Changing the shapes of bond pads
    • H10W72/01953—Changing the shapes of bond pads by etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07221—Aligning
    • H10W72/07227—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07255—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/227—Multiple bumps having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H10W72/2528—Intermetallic compounds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/261—Functions other than electrical connecting
    • H10W72/263—Providing mechanical bonding or support, e.g. dummy bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/261—Functions other than electrical connecting
    • H10W72/267—Multiple bump connectors having different functions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/281—Auxiliary members
    • H10W72/285—Alignment aids, e.g. alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
CN2008801227000A 2007-12-28 2008-12-10 具有限制部件的三维半导体管芯结构及其制造方法 Expired - Fee Related CN101911289B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/966,077 US7811932B2 (en) 2007-12-28 2007-12-28 3-D semiconductor die structure with containing feature and method
US11/966,077 2007-12-28
PCT/US2008/086174 WO2009085609A2 (en) 2007-12-28 2008-12-10 3-d semiconductor die structure with containing feature and method

Publications (2)

Publication Number Publication Date
CN101911289A CN101911289A (zh) 2010-12-08
CN101911289B true CN101911289B (zh) 2012-10-03

Family

ID=40797182

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008801227000A Expired - Fee Related CN101911289B (zh) 2007-12-28 2008-12-10 具有限制部件的三维半导体管芯结构及其制造方法

Country Status (7)

Country Link
US (2) US7811932B2 (enExample)
EP (1) EP2232549B1 (enExample)
JP (1) JP5234696B2 (enExample)
KR (1) KR101558194B1 (enExample)
CN (1) CN101911289B (enExample)
TW (1) TWI470746B (enExample)
WO (1) WO2009085609A2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7612443B1 (en) * 2003-09-04 2009-11-03 University Of Notre Dame Du Lac Inter-chip communication
US8293587B2 (en) 2007-10-11 2012-10-23 International Business Machines Corporation Multilayer pillar for reduced stress interconnect and method of making same
US8441123B1 (en) * 2009-08-13 2013-05-14 Amkor Technology, Inc. Semiconductor device with metal dam and fabricating method
EP2398046A1 (en) * 2010-06-18 2011-12-21 Nxp B.V. Integrated circuit package with a copper-tin joining layer and manufacturing method thereof
DE102010040065B4 (de) * 2010-08-31 2015-07-23 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verspannungsreduktion in einem Chipgehäuse unter Anwendung eines Chip-Gehäuse-Verbindungsschemas bei geringer Temperatur
US8907485B2 (en) 2012-08-24 2014-12-09 Freescale Semiconductor, Inc. Copper ball bond features and structure
US8907488B2 (en) * 2012-12-28 2014-12-09 Broadcom Corporation Microbump and sacrificial pad pattern
KR102052326B1 (ko) * 2014-12-17 2019-12-05 알파 어셈블리 솔루션스 인크. 다이 및 클립 부착 방법
US9713264B2 (en) 2014-12-18 2017-07-18 Intel Corporation Zero-misalignment via-pad structures
US10076034B2 (en) * 2016-10-26 2018-09-11 Nanya Technology Corporation Electronic structure
US10475736B2 (en) 2017-09-28 2019-11-12 Intel Corporation Via architecture for increased density interface
US10217718B1 (en) * 2017-10-13 2019-02-26 Denselight Semiconductors Pte. Ltd. Method for wafer-level semiconductor die attachment
JP7251951B2 (ja) * 2018-11-13 2023-04-04 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
US11862593B2 (en) 2021-05-07 2024-01-02 Microsoft Technology Licensing, Llc Electroplated indium bump stacks for cryogenic electronics

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120225A (ja) 1992-09-30 1994-04-28 Nippon Telegr & Teleph Corp <Ntt> 光モジュールの製造方法
KR19980025889A (ko) * 1996-10-05 1998-07-15 김광호 중합체층이 개재된 반도체 칩과 기판 간의 범프 접속 구조
US6365967B1 (en) * 1999-05-25 2002-04-02 Micron Technology, Inc. Interconnect structure
CN1976560A (zh) * 2005-11-29 2007-06-06 三星电机株式会社 使用焊膏凸块的基板和多层印刷电路板及其制造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06310565A (ja) * 1993-04-20 1994-11-04 Fujitsu Ltd フリップチップボンディング方法
US5767580A (en) * 1993-04-30 1998-06-16 Lsi Logic Corporation Systems having shaped, self-aligning micro-bump structures
US5903059A (en) * 1995-11-21 1999-05-11 International Business Machines Corporation Microconnectors
JP2845847B2 (ja) * 1996-11-12 1999-01-13 九州日本電気株式会社 半導体集積回路
US6965166B2 (en) * 1999-02-24 2005-11-15 Rohm Co., Ltd. Semiconductor device of chip-on-chip structure
US6586266B1 (en) * 1999-03-01 2003-07-01 Megic Corporation High performance sub-system design and assembly
US7087458B2 (en) * 2002-10-30 2006-08-08 Advanpack Solutions Pte. Ltd. Method for fabricating a flip chip package with pillar bump and no flow underfill
US20070152025A1 (en) * 2004-03-02 2007-07-05 Fuji Electric Holdings Co., Ltd. Electronic part mounting method
JP4331053B2 (ja) * 2004-05-27 2009-09-16 株式会社東芝 半導体記憶装置
US7348210B2 (en) * 2005-04-27 2008-03-25 International Business Machines Corporation Post bump passivation for soft error protection
US7781886B2 (en) * 2005-06-14 2010-08-24 John Trezza Electronic chip contact structure
US7135771B1 (en) * 2005-06-23 2006-11-14 Intel Corporation Self alignment features for an electronic assembly
US7332423B2 (en) * 2005-06-29 2008-02-19 Intel Corporation Soldering a die to a substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120225A (ja) 1992-09-30 1994-04-28 Nippon Telegr & Teleph Corp <Ntt> 光モジュールの製造方法
KR19980025889A (ko) * 1996-10-05 1998-07-15 김광호 중합체층이 개재된 반도체 칩과 기판 간의 범프 접속 구조
US6365967B1 (en) * 1999-05-25 2002-04-02 Micron Technology, Inc. Interconnect structure
CN1976560A (zh) * 2005-11-29 2007-06-06 三星电机株式会社 使用焊膏凸块的基板和多层印刷电路板及其制造方法

Also Published As

Publication number Publication date
JP5234696B2 (ja) 2013-07-10
KR20100102132A (ko) 2010-09-20
EP2232549B1 (en) 2018-09-19
JP2011508451A (ja) 2011-03-10
KR101558194B1 (ko) 2015-10-07
TWI470746B (zh) 2015-01-21
WO2009085609A2 (en) 2009-07-09
WO2009085609A3 (en) 2009-09-03
US20090166888A1 (en) 2009-07-02
EP2232549A2 (en) 2010-09-29
EP2232549A4 (en) 2011-04-06
TW200939413A (en) 2009-09-16
CN101911289A (zh) 2010-12-08
US7811932B2 (en) 2010-10-12
US20100327440A1 (en) 2010-12-30
US8581383B2 (en) 2013-11-12

Similar Documents

Publication Publication Date Title
CN101911289A (zh) 具有限制部件的三维半导体管芯结构及方法
US12476206B2 (en) Seal ring for hybrid-bond
TWI705508B (zh) 半導體元件及其製造方法
US10943873B2 (en) Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same
CN101728362B (zh) 三维集成电路的堆叠接合界面结构
US12469808B2 (en) Semiconductor package and manufacturing method thereof
CN110379717A (zh) 连接件结构及其形成方法
US9646944B2 (en) Alignment structures and methods of forming same
US20050082552A1 (en) Large bumps for optical flip chips
DE102020119159B4 (de) Bondungsstruktur und Verfahren zur Bildung derselben
TWI890101B (zh) 封裝件結構和其形成方法
US20170301562A1 (en) Semiconductor Structure and Method of Forming
CN119833490A (zh) 封装结构及其形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Texas in the United States

Patentee after: NXP America Co Ltd

Address before: Texas in the United States

Patentee before: Fisical Semiconductor Inc.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20121003

Termination date: 20191210