JP2011146701A - 酸化物層を有する半導体部品 - Google Patents
酸化物層を有する半導体部品 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 184
- 229910052801 chlorine Inorganic materials 0.000 claims abstract description 67
- 239000000460 chlorine Substances 0.000 claims abstract description 66
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims description 61
- 230000008569 process Effects 0.000 claims description 46
- 230000004888 barrier function Effects 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 claims description 14
- 238000007254 oxidation reaction Methods 0.000 claims description 14
- 239000013078 crystal Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 230000001590 oxidative effect Effects 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 210000000746 body region Anatomy 0.000 claims 1
- 239000010410 layer Substances 0.000 description 114
- 125000001309 chloro group Chemical group Cl* 0.000 description 18
- 239000007789 gas Substances 0.000 description 18
- 238000004519 manufacturing process Methods 0.000 description 8
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 5
- 238000000137 annealing Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 150000001804 chlorine Chemical class 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000002585 base Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
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Abstract
【解決手段】 酸化物層を有する半導体部品。一実施形態は、第1の半導体領域と第2の半導体領域とを含む。酸化物層は、第1および第2の半導体領域間に配置される。第1の半導体領域および酸化物層が第1の半導体−酸化物界面を形成する。第2の半導体領域および酸化物層が第2の半導体−酸化物界面を形成する。酸化物層は塩素濃度を有し、塩素濃度は、第1の半導体−酸化物界面の領域における第1の極大点と、第2の半導体−酸化物界面の領域における第2の極大点とを有する。
【選択図】図1
Description
2 酸化物層
3 半導体領域
12 第1の半導体−酸化物界面
13 第2の半導体−酸化物界面
21 トレンチ
100 半導体本体
Claims (25)
- 第1の半導体領域および第2の半導体領域と、
前記第1の半導体領域と前記第2の半導体領域との間に配置された酸化物層と、を含み、第1の半導体領域および前記酸化物層が第1の半導体−酸化物界面を形成し、第2の半導体領域および前記酸化物層が第2の半導体−酸化物界面を形成し、
前記酸化物層が塩素濃度を有し、前記塩素濃度が、前記第1の半導体−酸化物界面の領域における第1の極大点と、前記第2の半導体−酸化物界面の領域における第2の極大点とを有する、半導体部品。 - 前記第1および第2の極大点領域における塩素濃度が1019cm−3〜2・1021cm−3である、請求項1に記載の半導体部品。
- 前記塩素濃度が、前記第1の半導体−酸化物界面と前記第2の半導体−酸化物界面との間に、前記第1の極大点および前記第2の極大点未満の最小を有し、最小の塩素濃度が1015cm−3〜1018cm−3である、請求項1に記載の半導体部品。
- 前記酸化物層が、前記第1および第2の半導体−酸化物界面間の酸化物層の寸法である厚さを有し、当該厚さが10nm〜1μmである、請求項1に記載の半導体部品。
- 前記第1および第2の半導体領域がシリコン領域である、請求項1に記載の半導体部品。
- 前記第1および第2の半導体領域が単結晶半導体領域である、請求項1に記載の半導体部品。
- 第1の半導体領域および第2の半導体領域と、
前記第1の半導体領域と前記第2の半導体領域との間に配置された酸化物層と、を含み、第1の半導体領域および前記酸化物層が第1の半導体−酸化物界面を形成し、第2の半導体領域および前記酸化物層が第2の半導体−酸化物界面を形成し、
前記酸化物層が塩素濃度を有し、前記塩素濃度が、前記第1の半導体−酸化物界面の領域における第1の極大点と、前記第2の半導体−酸化物界面の領域における第2の極大点とを有し、
前記第1および第2の半導体領域ならびに前記酸化物層が、第1の表面を有する半導体本体に配置され、
前記酸化物層が前記半導体本体の表面まで延在し、
障壁が、前記表面に配置され、前記表面まで延在する前記酸化物層のセクションを少なくとも部分的に覆う、半導体部品。 - 前記障壁がシリコン層または窒化物層を含む、請求項7に記載の半導体部品。
- 前記障壁が、異なる材料からなる少なくとも2つの層を有する層スタックを含む、請求項7に記載の半導体部品。
- 前記障壁が、少なくとも1つの酸化物層と少なくとも1つの窒化物層とを含む、請求項9に記載の半導体部品。
- 前記第1および第2の半導体領域が能動部品領域である、請求項1に記載の半導体部品。
- 第1の半導体領域および第2の半導体領域と、
前記第1の半導体領域と前記第2の半導体領域との間に配置された酸化物層と、を含み、第1の半導体領域および前記酸化物層が第1の半導体−酸化物界面を形成し、第2の半導体領域および前記酸化物層が第2の半導体−酸化物界面を形成し、
前記酸化物層が塩素濃度を有し、前記塩素濃度が、前記第1の半導体−酸化物界面の領域における第1の極大点と、前記第2の半導体−酸化物界面の領域における第2の極大点とを有し、
前記第1の半導体領域が前記半導体部品のドリフト領域を形成し、前記第2の半導体領域がドリフト制御領域を形成し、
前記半導体部品が、
前記ドリフト領域と隣接し、整流素子を介して前記ドリフト制御領域に連結されるドレイン領域と、
前記ドレイン領域から距離をおいて配置される少なくとも1つの制御構造と、をさらに含む、半導体部品。 - 前記制御構造が、
ソースゾーンと、
前記ソースゾーンと前記ドリフトゾーンとの間に配置された本体ゾーンと、
前記本体ゾーンに隣接して配置され、ゲート誘電体によって前記本体ゾーンから絶縁されたゲート電極と、を含む、請求項12に記載の半導体部品。 - 前記ドリフト制御領域に接続されたコンデンサをさらに含む、請求項13に記載の半導体部品。
- 前記コンデンサが、前記ドリフト制御領域とソースおよび本体領域のうちの一方との間に接続されている、請求項14に記載の半導体部品。
- 第1の表面を有する半導体本体を提供し、
表面から半導体本体まで延在する、トレンチ表面を有する少なくとも1つのトレンチを形成し、
塩素の存在下で前記トレンチ表面にて前記半導体本体を熱的に酸化させることで、前記トレンチに酸化物層を形成することを含む、半導体部品の形成方法。 - 少なくとも前記少なくとも1つのトレンチが形成される領域における前記半導体本体が、単結晶半導体材料で形成される、請求項16に記載の方法。
- 前記半導体材料がシリコンである、請求項17に記載の方法。
- 完全な熱酸化プロセスの間に塩素が存在する、請求項16に記載の方法。
- 前記熱酸化プロセスの間に一時的に塩素が存在する、請求項16に記載の方法。
- 前記酸化プロセスの開始時に塩素が存在せず、塩素は開始時よりも後で存在する、請求項20に記載の方法。
- 前記塩素含有ガスの濃度が、酸化環境におけるプロセスガスの1%〜8%または2%〜8%である、請求項16に記載の方法。
- 前記塩素含有ガスの濃度が前記酸化プロセスの間に変動する、請求項22に記載の方法。
- 少なくとも1つの窒化物層を形成することを含めて、前記酸化物層上の第1の表面に障壁を形成することをさらに含む、請求項16に記載の方法。
- 第1の表面を有する第1の半導体本体を提供し、
前記第1の表面に塩素濃度を有し、前記第1の半導体本体とで第1の半導体−酸化物界面を形成する酸化物層を、塩素の存在下で前記第1の表面に沿って前記第1の半導体本体を熱的に酸化させることで形成し、
前記酸化物層とで第2の半導体−酸化物界面を形成する第2の半導体本体を、前記酸化物層にボンディングし、
前記第1および第2の半導体本体ならびに前記酸化物層を含むアレンジメントを、前記酸化物層の塩素濃度の第1および第2の極大点が前記第1および第2の半導体−酸化物界面の領域で生じるように選択した加熱プロセスの温度と時間で加熱することを含む、半導体部品の形成方法。
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US11289330B2 (en) * | 2019-09-30 | 2022-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator (SOI) substrate and method for forming |
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04157765A (ja) * | 1990-10-20 | 1992-05-29 | Nippon Telegr & Teleph Corp <Ntt> | 絶縁ゲート型電界効果トランジスタ及びその製法 |
JP2000150636A (ja) * | 1998-11-06 | 2000-05-30 | Nec Corp | 半導体装置とその製造方法 |
US20050112888A1 (en) * | 2003-03-28 | 2005-05-26 | International Business Machines Corporation | Semiconductor metal contamination reduction for ultra-thin gate dielectrics |
JP2005197684A (ja) * | 2004-12-21 | 2005-07-21 | Sanyo Electric Co Ltd | 半導体装置 |
JP2006310350A (ja) * | 2005-04-26 | 2006-11-09 | Ishikawajima Harima Heavy Ind Co Ltd | 素子間分離領域の形成方法 |
JP2007158371A (ja) * | 2007-02-02 | 2007-06-21 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
JP2009503830A (ja) * | 2005-07-27 | 2009-01-29 | インフィネオン テクノロジーズ オーストリア アクチエンゲゼルシャフト | ドリフト領域とドリフト制御領域とを有する半導体素子 |
JP2009212503A (ja) * | 2008-02-04 | 2009-09-17 | Semiconductor Energy Lab Co Ltd | Soi基板の作製方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5498577A (en) * | 1994-07-26 | 1996-03-12 | Advanced Micro Devices, Inc. | Method for fabricating thin oxides for a semiconductor technology |
US5891809A (en) * | 1995-09-29 | 1999-04-06 | Intel Corporation | Manufacturable dielectric formed using multiple oxidation and anneal steps |
JP3729955B2 (ja) * | 1996-01-19 | 2005-12-21 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US6100562A (en) * | 1996-03-17 | 2000-08-08 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
US6191463B1 (en) * | 1997-07-15 | 2001-02-20 | Kabushiki Kaisha Toshiba | Apparatus and method of improving an insulating film on a semiconductor device |
JP2003204063A (ja) * | 2002-01-10 | 2003-07-18 | Toshiba Corp | 半導体装置及びその製造方法 |
US8461648B2 (en) * | 2005-07-27 | 2013-06-11 | Infineon Technologies Austria Ag | Semiconductor component with a drift region and a drift control region |
DE102005047102B3 (de) * | 2005-09-30 | 2007-05-31 | Infineon Technologies Ag | Halbleiterbauelement mit pn-Übergang |
JP5032145B2 (ja) * | 2006-04-14 | 2012-09-26 | 株式会社東芝 | 半導体装置 |
CN101669193B (zh) * | 2007-04-27 | 2012-02-15 | 株式会社半导体能源研究所 | Soi衬底及其制造方法和半导体器件 |
US7875532B2 (en) * | 2007-06-15 | 2011-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Substrate for manufacturing semiconductor device and manufacturing method thereof |
US20090032861A1 (en) * | 2007-07-30 | 2009-02-05 | Zhong Dong | Nonvolatile memories with charge trapping layers containing silicon nitride with germanium or phosphorus |
JP2009076637A (ja) * | 2007-09-20 | 2009-04-09 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
JP2009272365A (ja) * | 2008-05-01 | 2009-11-19 | Renesas Technology Corp | 半導体装置の製造方法 |
JP5548395B2 (ja) * | 2008-06-25 | 2014-07-16 | 株式会社半導体エネルギー研究所 | Soi基板の作製方法 |
-
2009
- 2009-12-17 US US12/640,974 patent/US20110147817A1/en not_active Abandoned
-
2010
- 2010-12-16 DE DE102010063271A patent/DE102010063271A1/de not_active Ceased
- 2010-12-17 JP JP2010281528A patent/JP5498929B2/ja not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04157765A (ja) * | 1990-10-20 | 1992-05-29 | Nippon Telegr & Teleph Corp <Ntt> | 絶縁ゲート型電界効果トランジスタ及びその製法 |
JP2000150636A (ja) * | 1998-11-06 | 2000-05-30 | Nec Corp | 半導体装置とその製造方法 |
US20050112888A1 (en) * | 2003-03-28 | 2005-05-26 | International Business Machines Corporation | Semiconductor metal contamination reduction for ultra-thin gate dielectrics |
JP2005197684A (ja) * | 2004-12-21 | 2005-07-21 | Sanyo Electric Co Ltd | 半導体装置 |
JP2006310350A (ja) * | 2005-04-26 | 2006-11-09 | Ishikawajima Harima Heavy Ind Co Ltd | 素子間分離領域の形成方法 |
JP2009503830A (ja) * | 2005-07-27 | 2009-01-29 | インフィネオン テクノロジーズ オーストリア アクチエンゲゼルシャフト | ドリフト領域とドリフト制御領域とを有する半導体素子 |
JP2007158371A (ja) * | 2007-02-02 | 2007-06-21 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
JP2009212503A (ja) * | 2008-02-04 | 2009-09-17 | Semiconductor Energy Lab Co Ltd | Soi基板の作製方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20210038835A (ko) * | 2019-09-30 | 2021-04-08 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Soi(semiconductor-on-insulator) 기판 및 형성 방법 |
KR102522808B1 (ko) * | 2019-09-30 | 2023-04-17 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Soi(semiconductor-on-insulator) 기판 및 형성 방법 |
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