JP6022777B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 210000000746 body region Anatomy 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 22
- 238000005468 ion implantation Methods 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 5
- 230000001133 acceleration Effects 0.000 claims description 3
- 238000009751 slip forming Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 71
- 230000015556 catabolic process Effects 0.000 description 21
- 239000012535 impurity Substances 0.000 description 17
- 150000004767 nitrides Chemical class 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 230000007774 longterm Effects 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910001416 lithium ion Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003446 memory effect Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
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Description
第1導電型の半導体基板に、第2導電型の埋め込み層を形成する工程と、
前記埋め込み層上に第2導電型のエピタキシャル層を形成する工程と、
前記エピタキシャル層内にトレンチを形成する工程と、
前記トレンチの底面の下方であって、前記埋め込み層とエピタキシャル層との境界面より下に分布の中心を有する、第1導電型の相殺領域を、前記埋め込み層の導電型を打ち消すために形成する工程と、
前記エピタキシャル層内の前記トレンチの側面周辺に、第1導電型のボディ領域を形成し、同時に前記トレンチの底面の下方に第1導電型のトレンチ底面下方領域を前記相殺領域に連続して形成する工程と、
前記トレンチの内壁にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜に接し、前記トレンチ内に多結晶シリコンを充填しゲート電極を形成する工程と、
前記ボディ領域表面に第2導電型のソース領域を形成する工程と、
前記ボディ領域表面に第1導電型のボディコンタクト領域を形成する工程と、
からなる半導体装置の製造方法とした。
第1導電型の半導体基板と、
前記半導体基板の表面に設けられた第2導電型の埋め込み層と、
前記埋め込み層上に設けられた第2導電型のエピタキシャル層と、
前記エピタキシャル層の表面から前記エピタキシャル層内に設けられたトレンチと、
前記トレンチの底面の下方であって、前記埋め込み層とエピタキシャル層との境界面より下に分布の中心を有する、前記埋め込み層の導電型を打ち消すための第1導電型の相殺領域と、
前記エピタキシャル層内の前記トレンチの側面周辺に設けられた第1導電型のボディ領域と、
前記トレンチの底面から前記相殺領域に連続して設けられた第1導電型のトレンチ底面下方領域と、
前記トレンチの内壁に設けられたゲート絶縁膜と、
前記ゲート絶縁膜に接し、前記トレンチ内を充填している多結晶シリコンのゲート電極と、
前記ボディ領域表面に設けられた第2導電型のソース領域と、
前記ボディ領域表面に設けられた第1導電型のボディコンタクト領域と、
からなる半導体装置とした。
第1導電型の半導体基板に、第2導電型のエピタキシャル層を形成する工程と、
前記第2導電型のエピタキシャル層内にトレンチを形成する工程と、
前記半導体基板の表面および前記トレンチの内壁に犠牲酸化膜を形成する工程と、
前記犠牲酸化膜が形成されたトレンチ内に、前記トレンチの深さの半分以下となる厚みを有するレジストを配置する工程と、
前記犠牲酸化膜および前記レジストを通して、前記エピタキシャル層と前記半導体基板との境界に第2導電型の埋め込み層をイオン注入により形成する工程と、
前記レジストを除去した後に、前記エピタキシャル層内の前記トレンチの側面周辺に第1導電型のボディ領域を形成し、同時に前記トレンチの底面の下方に第1導電型のトレンチ底面下方領域を前記埋め込み層に連続して形成する工程と、
前記犠牲酸化膜を除去し、前記トレンチ領域の内壁にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜に接し、前記トレンチ内に多結晶シリコンを充填しゲート電極を形成する工程と、
前記ボディ領域表面に第2導電型のソース領域を形成する工程と、
前記ボディ領域表面に第1導電型のボディコンタクト領域を形成する工程と、
からなる半導体装置の製造方法とした。
第1導電型の半導体基板と、
前記半導体基板の表面に設けられた第2導電型の埋め込み層と、
前記埋め込み層上に設けられた第2導電型のエピタキシャル層と、
前記エピタキシャル層の表面から前記エピタキシャル層内に設けられたトレンチと、
前記エピタキシャル層内の前記トレンチの側面周辺に設けられた第1導電型のボディ領域と、
前記トレンチの底面から前記埋め込み層にかけて設けられた第1導電型のトレンチ底面下方領域と、
前記トレンチの内壁に設けられたゲート絶縁膜と、
前記ゲート絶縁膜に接し、前記トレンチ内を充填している多結晶シリコンのゲート電極と、
前記ボディ領域表面に設けられた第2導電型のソース領域と、
前記ボディ領域表面に設けられた第1導電型のボディコンタクト領域と、
からなり、
前記埋め込み層は、前記トレンチ底面下方領域の下となる部分においては前記エピタキシャル層の下となる部分よりも前記半導体基板に向かって深い位置に設けられている半導体装置とした。
まずP型半導体基板1を用意し、図1(a)に示すようにドレインとなる、N型高濃度埋め込み層2をイオン注入法により形成する。そして、N型高濃度埋め込み層2上にエピタキシャル法によりN−Epi層3を形成する。N型高濃度埋め込み層2は、N型縦型トレンチMOSFETのドレイン抵抗を極力抑制するため、5×1018〜1×1019/cm3の濃度となるように、Sb(アンチモン)、あるいはAs(砒素)、あるいはP(リン)をドープすることにより形成する。またN−Epi層3は、MOSFETの耐圧や駆動電流など、製造する半導体集積装置に求められる性能から決まり、例えば、5×1016〜2×1017/cm3の濃度で4.5μm〜5.0μm程度の厚さとすることができる。
次に図1(e)において、P型ボディ領域4の上側表面に、N型ソース高濃度領域6を形成するためのイオン注入を行なう。N型ソース高濃度領域6を形成するためには、例えばAsをシート抵抗低減のため、好ましくは1×1018〜1×1019/cm3程度の濃度となるドーズ量でイオン注入する。もちろん、Asの代わりにP(リン)を高濃度に注入しても良い。
最後に、図示していないが、層間絶縁膜を形成し、層間絶縁膜に電極形成用の穴であるコンタクトホールを設け、アルミの電極を形成する。
第2の実施例のトレンチMOSFETの工程順断面図を図2に示す。
図2(a)に示したようにP型半導体基板1上にエピタキシャル法によりを形成する。N−Epi層3は、MOSFETの耐圧や駆動電流など、作成する半導体集積装置に求められる性能から決まるが、5×1016〜2×1017/cm3の濃度で4.5μm〜5.0μm程度の厚さとすることも可能である。次に同図(a)に示したようにN型の縦型MOSFET形成予定領域に、P型半導体基板1の内部に向かって窒化膜をハードマスクにして異方性エッチングを行い、トレンチ8を形成する。このときトレンチ8の深さは、N−Epi層3の厚さよりも浅く、1.4μm〜2.0μmであり所望のトランジスタ・ドレイン耐圧により適宜設定することができる。
次に図2(e)において、P型ボディ領域4の上側表面に、N型ソース高濃度領域6を形成するためのイオン注入を行なう。N型ソース高濃度領域6を形成するためには、例えばAsをシート抵抗低減のため、好ましくは1×1018〜1×1019/cm3程度のドーズ量でイオン注入する。もちろん、P(リン)を高濃度に注入しても良い。
最後に、図示していないが、層間絶縁膜を形成し、層間絶縁膜に電極形成用の穴であるコンタクトホールを設け、アルミの電極を形成する。
トレンチの形状を利用してP型不純物を注入することで、トレンチ底面下方領域5の導電型を逆にし、さらに、ゲート・ドレイン間の距離を伸ばすことで、ここに印加される電界を緩和でき耐圧を向上させることが可能となる。
2 N型埋め込み層
3 N−Epi層
4 P型ボディ領域
5 トレンチ底面下方領域
6 N型ソース高濃度領域
7 P型ボディコンタクト領域
8 トレンチ
9 犠牲酸化膜
10 ゲート絶縁膜
11 ゲート電極
12 相殺領域
13 レジスト
14 窒化膜
Claims (5)
- 第1導電型の半導体基板に、第2導電型の埋め込み層を形成する工程と、
前記埋め込み層上に第2導電型のエピタキシャル層を形成する工程と、
前記エピタキシャル層内にトレンチを形成する工程と、
前記トレンチの底面の下方であって、前記埋め込み層とエピタキシャル層との境界面より下に分布の中心を有する、第1導電型の相殺領域を、前記埋め込み層の導電型を打ち消すために部分的に形成する工程と、
前記エピタキシャル層内の前記トレンチの側面周辺に、第1導電型のボディ領域を形成し、同時に前記トレンチの底面の下方に第1導電型のトレンチ底面下方領域を前記相殺領域に連続して形成する工程と、
前記トレンチの内壁にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜に接し、前記トレンチ内に多結晶シリコンを充填しゲート電極を形成する工程と、
前記ボディ領域表面に第2導電型のソース領域を形成する工程と、
前記ボディ領域表面に第1導電型のボディコンタクト領域を形成する工程と、
からなる半導体装置の製造方法。 - 前記第2導電型のエピタキシャル層は5×1016/cm3から2×1017/cm3の濃度で4.5μmから5.0μmの厚さを有する請求項1記載の半導体装置の製造方法。
- 前記ボディ領域と前記トレンチ底面下方領域を同時に形成する工程は、ボロンを用いたイオン注入であり、その条件は、加速エネルギー:150KeV〜250KeV、濃度:1×1017/cm3〜5×1017/cm3、イオン注入角度:3°〜10°、および90°毎の4ステップ回転注入である請求項1記載の半導体装置の製造方法。
- 第1導電型の半導体基板に、第2導電型のエピタキシャル層を形成する工程と、
前記第2導電型のエピタキシャル層内にトレンチを形成する工程と、
前記半導体基板の表面および前記トレンチの内壁に犠牲酸化膜を形成する工程と、
前記犠牲酸化膜が形成されたトレンチ内に、前記トレンチの深さの半分以下となる厚みを有するレジストを配置する工程と、
前記犠牲酸化膜および前記レジストを通して、前記エピタキシャル層と前記半導体基板との境界に第2導電型の埋め込み層をイオン注入により形成する工程と、
前記レジストを除去した後に、前記エピタキシャル層内の前記トレンチの側面周辺に第1導電型のボディ領域を形成し、同時に前記トレンチの底面の下方に第1導電型のトレンチ底面下方領域を前記埋め込み層に連続して形成する工程と、
前記犠牲酸化膜を除去し、前記トレンチ領域の内壁にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜に接し、前記トレンチ内に多結晶シリコンを充填しゲート電極を形成する工程と、
前記ボディ領域表面に第2導電型のソース領域を形成する工程と、
前記ボディ領域表面に第1導電型のボディコンタクト領域を形成する工程と、
からなる半導体装置の製造方法。 - 前記埋め込み層をイオン注入により形成する工程は、イオン注入角度が0°である請求項4記載の半導体装置の製造方法。
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