JP2011096885A - 半導体素子およびその製造方法 - Google Patents
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Abstract
【解決手段】この半導体素子1は、第1方向(A方向)および第2方向(B方向)に平行な主表面を有するとともに第1方向に沿って延びる段差部2aが形成された窒化物系半導体からなる基板2と、基板2上に形成され、窒化物系半導体からなる下地層3、第1半導体層4および第2半導体層5とを備える。そして、下地層3および第2半導体層5の無歪みの状態における第2方向の格子定数は、それぞれ、基板2の無歪みの状態における第2方向の格子定数よりも大きく、下地層3および第2半導体層5の基板2の主表面上に形成された状態における第2方向の格子定数は、それぞれ、基板2の第2方向の格子定数よりも大きい。
【選択図】図1
Description
まず、図5を参照して、本発明の第1実施形態による窒化物系半導体レーザ素子100の構造について説明する。
図9を参照して、第2実施形態について説明する。この第2実施形態による窒化物系半導体レーザ素子200の製造プロセスでは、上記第1実施形態と異なり、約5μmの深さを有する溝部11dが予め形成されたn型GaN基板10を用いて半導体素子層を積層する場合について説明する。なお、図中において、上記第1実施形態と同様の構成には、上記第1実施形態と同じ符号を付して図示している。
図10を参照して、第3実施形態について説明する。この第3実施形態による窒化物系半導体レーザ素子300の製造プロセスでは、上記第2実施形態と異なり、上面(C2側の表面)から内部に向かって開口幅が広がる方向に傾斜する側面12fを有する溝部12dが形成されたn型GaN基板10を用いて半導体素子層を積層する場合について説明する。なお、図中において、上記第2実施形態と同様の構成には、上記第2実施形態と同じ符号を付して図示している。
まず、図11を参照して、第4実施形態による窒化物系半導体レーザ素子400の構造について説明する。なお、図中において、上記第1実施形態と同様の構成には、上記第1実施形態と同じ符号を付して図示している。
図14を参照して、第5実施形態について説明する。この第5実施形態による窒化物系半導体レーザ素子500では、上記第1実施形態と異なる材料からなるn型クラッド層531を用いて窒化物系半導体層530を形成する場合について説明する。なお、図中において、上記第1実施形態と同様の構成には、上記第1実施形態と同じ符号を付して図示している。
図15を参照して、第6実施形態について説明する。この第6実施形態による窒化物系半導体レーザ素子600では、上記第5実施形態と異なる材料からなる下地層620およびn型クラッド層631を用いて、n型GaN基板10の表面上に窒化物系半導体層630を形成する場合について説明する。なお、図中において、上記第5実施形態と同様の構成には、上記第5実施形態と同じ符号を付して図示している。
図16を参照して、第7実施形態について説明する。この第7実施形態による窒化物系半導体レーザ素子700では、上記第1実施形態と異なり、(1−100)面の主表面を有するn型GaN基板710を用いて窒化物系半導体層30を形成する場合について説明する。なお、図中において、上記第1実施形態と同様の構成には、上記第1実施形態と同じ符号を付して図示している。
2a、10a、11a、12a、70a 段差部
2b、10b、70b、710b テラス部(段差部以外の領域)
3、20、80、620 下地層
4 第1半導体層
5 第2半導体層
10、710 n型GaN基板(基板)
31、91、531、631 n型クラッド層(第1半導体層)
32、92 n側キャリアブロック層(第2半導体層)
33、93、533 活性層(第2半導体層)
34、94、534 p側光ガイド層(第2半導体層)
35、95、535 p側キャリアブロック層(第2半導体層)
36、96、536 p型クラッド層(第2半導体層)
37、97 p側コンタクト層(第2半導体層)
70 n型Al0.4Ga0.6N基板(基板)
Claims (7)
- 第1方向および前記第1方向と交差する第2方向に平行な主表面を有する窒化物系半導体からなる基板と、
前記主表面上に形成された窒化物系半導体からなる下地層と、
前記下地層の前記基板とは反対側の表面上に形成された窒化物系半導体からなる第1半導体層と、
前記第1半導体層の前記下地層とは反対側の表面上に形成された窒化物系半導体からなる第2半導体層とを備え、
前記主表面上には、前記第1方向に沿って延びる段差部が形成されており、
前記下地層および前記第2半導体層の無歪みの状態における前記第2方向の格子定数は、それぞれ、前記基板の無歪みの状態における前記第2方向の格子定数よりも大きく、
前記下地層および前記第2半導体層の前記主表面上に形成された状態における前記第2方向の格子定数は、それぞれ、前記基板の前記第2方向の格子定数よりも大きい、半導体素子。 - 前記下地層は、前記第1方向の歪みが前記第2方向の歪みよりも大きい状態で、前記基板の主表面上に形成されている、請求項1に記載の半導体素子。
- 前記下地層の厚みは、前記第1半導体層の厚みよりも大きい、請求項1または2に記載の半導体素子。
- 前記基板は、Inを含まず、前記下地層および前記第2半導体層は、Inを含む、請求項1〜3のいずれか1項に記載の半導体素子。
- 前記段差部以外の領域における前記下地層の厚みは、前記段差部の高さよりも小さい、請求項1〜4のいずれか1項に記載の半導体素子。
- 前記第2半導体層は、井戸層を有する活性層を含み、
前記井戸層の無歪みの状態における前記第2方向の格子定数は、前記基板の無歪みの状態における前記第2方向の格子定数よりも大きい、請求項1〜5のいずれか1項に記載の半導体素子。 - 第1方向および前記第1方向と交差する第2方向に平行な主表面を有する窒化物系半導体からなる基板の前記主表面上に、前記第1方向に沿って延びる段差部を形成する工程と、
前記主表面上に窒化物系半導体からなる下地層を形成する工程と、
前記下地層の前記基板とは反対側の表面上に窒化物系半導体からなる第1半導体層を形成する工程と、
前記第1半導体層の前記下地層とは反対側の表面上に窒化物系半導体からなる第2半導体層を形成する工程とを備え、
前記下地層および前記第2半導体層の無歪みの状態における前記第2方向の格子定数は、それぞれ、前記基板の無歪みの状態における前記第2方向の格子定数よりも大きく、
前記下地層を形成する工程、および、前記第2半導体層を形成する工程は、それぞれ、前記下地層および前記第2半導体層の前記第2方向の格子定数が前記基板の前記第2方向の格子定数よりも大きくなるように形成する工程を含む、半導体素子の製造方法。
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