JP2011034999A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2011034999A JP2011034999A JP2009176867A JP2009176867A JP2011034999A JP 2011034999 A JP2011034999 A JP 2011034999A JP 2009176867 A JP2009176867 A JP 2009176867A JP 2009176867 A JP2009176867 A JP 2009176867A JP 2011034999 A JP2011034999 A JP 2011034999A
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- Prior art keywords
- electrode pad
- probe needle
- semiconductor device
- semiconductor
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Abstract
【解決手段】検査装置のプローブカードは、コイル型プローブ針とその内側に配置されたポゴピン型プローブ針とで構成されたケルビンコンタクト用プローブ針および2端子測定用プローブ針を備えている。ウエハのチップ領域1Aに形成された電極パッド2、3は、ケルビンコンタクト用プローブ針が接触する電極パッド3の面積をB、2端子測定用プローブ針が接触する電極パッド2の面積をAとしたとき、A≦B<2Aの関係にある。
【選択図】図3
Description
本実施の形態は、面実装型半導体パッケージの一種であるCSPの製造に適用したものであり、図1は、このCSPの製造工程を示す全体フロー図である。
前述の実施の形態1では、電源端子および出力端子である電極パッド3の面積を電極パッド2の面積の2倍よりも小さくし、現状のカンチタイプのプローブ針のピッチを小さくして、ケルビンコンタクトすることについて説明した。
図14(a)は、本実施の形態のケルビンコンタクト用プローブ針を示す側面図、図14(b)は、このケルビンコンタクト用プローブ針の先端部の拡大図である。
図18(a)は、本実施の形態のケルビンコンタクト用プローブ針を示す要部破断断面図、図18(b)は、(a)のD−D線に沿った断面図である。
1A チップ領域
1B 半導体チップ
2、3 電極パッド
4 パッシベーション膜
5 ポリイミド樹脂膜
6 再配線
7 ポリイミド樹脂膜
8 開口
9 UBM層
10 半田ボール
20 プローブカード
21 ケルビンコンタクト用プローブ針
22 コイル型プローブ針
23a ポゴピン型プローブ針
23b 2端子測定用プローブ針
25 コイル型プローブ針ガイド
26 第1配線基板
26a 配線
27 スペーサ
28 第2配線基板
30 メイン基板
30a、30b、30c 配線
31 導電性ゴム
32 ビアホール
33 ペースト半田
34a、34b、34c 電極
40 プローブカード
41 ケルビンコンタクト用プローブ針
41f フォース側プローブ針
41s センス側プローブ針
42 絶縁シート
51 ケルビンコンタクト用プローブ針
52a、52b ポゴピン型プローブ針
53 絶縁チューブ
54 コイルバネ
55a、55b 仕切り板
56 コイルバネ
60 配線基板
61 電極
62 Auワイヤ
63 モールド樹脂
64 半田ボール
65 カンチレバー型プローブ針
Claims (19)
- (a)主面が複数のチップ領域に区画された半導体ウエハを用意する工程と、
(b)前記複数のチップ領域のそれぞれに半導体集積回路を形成する工程と、
(c)前記複数のチップ領域のそれぞれの表面に、前記半導体集積回路に電気的に接続された第1電極パッドと第2電極パッドとを含む複数の電極パッドを形成する工程と、
(d)前記複数の電極パッドのそれぞれにプローブ針を接触することによって、前記半導体集積回路の電気特性検査を行う工程と、
(e)前記工程(d)の後、前記半導体ウエハをダイシングして前記複数のチップ領域のそれぞれを個片化することにより、複数の半導体チップを取得する工程と、
を含む半導体装置の製造方法であって、
前記工程(d)の前記電気特性検査は、前記第1電極パッドに2個のプローブ針を接触するケルビンコンタクト法を用いた電気特性検査を含み、
前記第1電極パッドの面積は、前記第2電極パッドの面積の2倍よりも小さいことを特徴とする半導体装置の製造方法。 - 前記第1電極パッドの面積をB、前記第2電極パッドの面積をAとしたとき、A≦B<2Aの関係が成立していることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記第1電極パッドに接触する前記2個のプローブ針は、カンチレバー型プローブ針を用いることを特徴とする請求項2記載の半導体装置の製造方法。
- 前記1電極パッドに接触するカンチレバー型プローブ針は、2本並べられた構造となっていることを特徴とする請求項3記載の半導体装置の製造方法。
- 前記第1電極パッドは、電源端子もしくは出力端子であることを特徴とする請求項4記載の半導体装置の製造方法。
- 前記ケルビンコンタクト法を用いた電気特性検査は、前記半導体集積回路を構成する素子のオン抵抗を測定する検査であることを特徴とする請求項5記載の半導体装置の製造方法。
- 前記半導体集積回路は、モータドライバ回路であることを特徴とする請求項6記載の半導体装置の製造方法。
- 前記第1電極パッドは、長方形であることを特徴とする請求項7記載の半導体装置の製造方法。
- 前記工程(d)と前記工程(e)との間に、前記第1電極パッドに半田ボールを電気的に接続する工程をさらに含むことを特徴とする請求項8記載の半導体装置の製造方法。
- 前記第1電極パッドに接触する前記2個のプローブ針は、プローブカードに支持されたコイル型プローブ針と、前記コイル型プローブ針の内側に配置され、前記プローブカードに支持されたポゴピン型プローブ針からなることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記ポゴピン型プローブ針は、フォース側プローブ針を構成し、前記コイル型プローブ針は、センス側プローブ針を構成し、
非作動時には、前記ポゴピン型プローブ針の先端部が、前記コイル型プローブ針の先端部よりも下方に突出していることを特徴とする請求項10記載の半導体装置の製造方法。 - 前記ポゴピン型プローブ針の表面、または前記コイル型プローブ針の表面には、前記電極パッドと接触する下端部を除いて絶縁コーティングが施されていることを特徴とする請求項10記載の半導体装置の製造方法。
- 前記プローブカードには、前記2個のプローブ針とは異なる第3の2端子測定用プローブ針が支持されており、
前記工程(d)の前記電気特性検査は、前記第2電極パッドに前記2端子測定用プローブ針を接触する電気特性検査を含むことを特徴とする請求項10記載の半導体装置の製造方法。 - (a)主面が複数のチップ領域に区画された半導体ウエハを用意する工程と、
(b)前記複数のチップ領域のそれぞれに半導体集積回路を形成する工程と、
(c)前記複数のチップ領域のそれぞれの表面に、前記半導体集積回路に電気的に接続された複数の電極パッドを形成する工程と、
(d)前記複数の電極パッドのそれぞれにプローブ針を接触することによって、前記半導体集積回路の電気特性検査を行う工程と、
(e)前記工程(d)の後、前記半導体ウエハをダイシングして前記複数のチップ領域のそれぞれを個片化することにより、複数の半導体チップを取得する工程と、
を含む半導体装置の製造方法であって、
前記工程(d)の前記電気特性検査は、前記複数の電極パッドのうちの所定の第1電極パッドに2個のプローブ針を接触するケルビンコンタクト法を用いた電気特性検査を含み、
前記第1電極パッドに接触する前記2個のプローブ針は、プローブカードに支持された第1カンチレバー型プローブ針と、絶縁体を介して前記第1カンチレバー型プローブ針の上部に配置され、前記プローブカードに支持された第2カンチレバー型プローブ針からなることを特徴とする半導体装置の製造方法。 - (a)主面が複数のチップ領域に区画された半導体ウエハを用意する工程と、
(b)前記複数のチップ領域のそれぞれに半導体集積回路を形成する工程と、
(c)前記複数のチップ領域のそれぞれの表面に、前記半導体集積回路に電気的に接続された複数の電極パッドを形成する工程と、
(d)前記複数の電極パッドのそれぞれにプローブ針を接触することによって、前記半導体集積回路の電気特性検査を行う工程と、
(e)前記工程(d)の後、前記半導体ウエハをダイシングして前記複数のチップ領域のそれぞれを個片化することにより、複数の半導体チップを取得する工程と、
を含む半導体装置の製造方法であって、
前記工程(d)の前記電気特性検査は、前記複数の電極パッドのうちの所定の第1電極パッドに2個のプローブ針を接触するケルビンコンタクト法を用いた電気特性検査を含み、
前記第1電極パッドに接触する前記2個のプローブ針は、プローブカードに支持された第1ポゴピン型プローブ針および第2ポゴピン型プローブ針とからなり、
前記第1ポゴピン型プローブ針および前記第2ポゴピン型プローブ針は、それぞれの中途部がクランク状に折り曲げられ、それぞれの先端部が前記中途部の上部よりも互いに近接して配置されていることを特徴とする半導体装置の製造方法。 - 半導体チップの主面に複数の回路と、
第1電極パッドおよび第2電極パッドを含み、前記複数の回路と電気的に接続された複数の電極パッドと、
を備え、
前記第1電極パッドは、ケルビンコンタクトされるパッドであって、
前記第1電極パッドの面積は、前記第2電極パッドの面積の2倍よりも小さいことを特徴とする半導体装置。 - 前記第1電極パッドの面積をB、前記第2電極パッドの面積をAとしたとき、A≦B<2Aの関係が成立していることを特徴とする請求項16記載の半導体装置。
- 前記第1電極パッドは、電源端子もしくは出力端子であることを特徴とする請求項17記載の半導体装置。
- 前記複数の回路は、モータドライバ回路を含むことを特徴とする請求項18記載の半導体装置。
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