JP5655705B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5655705B2 JP5655705B2 JP2011115652A JP2011115652A JP5655705B2 JP 5655705 B2 JP5655705 B2 JP 5655705B2 JP 2011115652 A JP2011115652 A JP 2011115652A JP 2011115652 A JP2011115652 A JP 2011115652A JP 5655705 B2 JP5655705 B2 JP 5655705B2
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- 239000004065 semiconductor Substances 0.000 title claims description 145
- 239000000523 sample Substances 0.000 claims description 84
- 230000002093 peripheral effect Effects 0.000 claims description 40
- 238000007689 inspection Methods 0.000 claims description 33
- 239000010410 layer Substances 0.000 description 25
- 239000000758 substrate Substances 0.000 description 20
- 239000011229 interlayer Substances 0.000 description 18
- 238000002161 passivation Methods 0.000 description 15
- 238000000034 method Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000002344 surface layer Substances 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
Claims (4)
- FET構造を有する複数の単位セルを含む半導体装置において、
各前記単位セルの前記FET構造が有するゲート電極に電気的に接続されるゲート電極配線と、
前記ゲート電極配線に電気的に接続されており各前記ゲート電極を外部接続するためのゲート電極パッドと、
前記ゲート電極配線に電気的に接続されており検査用プローブが接触されるプローブ用電極パッドと、
セル部と、
前記セル部を取り囲んでいると共に、前記セル部を電気的に保護する外周部と、
を備え、
前記セル部は、複数の前記単位セルが並列に配置されて構成されており、
前記プローブ用電極パッドは、前記セル部の外縁部上に設けられていると共に、前記セル部から前記外周部に向けて張り出している、
半導体装置。 - 前記ゲート電極配線は、前記セル部の外縁部に沿って配置されている、
請求項1に記載の半導体装置。 - 前記セル部の平面視形状は略四角形状であり、
前記プローブ用電極パッドは、前記セル部の4つの角部のうちの少なくとも一つの角部に設けられている、
請求項1又は2に記載の半導体装置。 - 複数の前記プローブ用電極パッドを備える、請求項1〜3の何れか一項記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011115652A JP5655705B2 (ja) | 2011-05-24 | 2011-05-24 | 半導体装置 |
PCT/JP2012/057052 WO2012160868A1 (ja) | 2011-05-24 | 2012-03-19 | 半導体装置 |
US13/477,855 US20120298994A1 (en) | 2011-05-24 | 2012-05-22 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011115652A JP5655705B2 (ja) | 2011-05-24 | 2011-05-24 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012244102A JP2012244102A (ja) | 2012-12-10 |
JP5655705B2 true JP5655705B2 (ja) | 2015-01-21 |
Family
ID=47216957
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011115652A Expired - Fee Related JP5655705B2 (ja) | 2011-05-24 | 2011-05-24 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20120298994A1 (ja) |
JP (1) | JP5655705B2 (ja) |
WO (1) | WO2012160868A1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9379048B2 (en) * | 2013-02-28 | 2016-06-28 | Semiconductor Components Industries, Llc | Dual-flag stacked die package |
JP6476000B2 (ja) * | 2015-02-17 | 2019-02-27 | 三菱電機株式会社 | 半導体装置および半導体モジュール |
US10475920B2 (en) * | 2015-04-22 | 2019-11-12 | Mitsubishi Electric Corporation | Semiconductor device and semiconductor device manufacturing method |
JP6641488B2 (ja) * | 2016-08-25 | 2020-02-05 | 三菱電機株式会社 | 半導体装置 |
JP2019145646A (ja) * | 2018-02-20 | 2019-08-29 | 株式会社東芝 | 半導体装置 |
JP7200488B2 (ja) * | 2018-03-19 | 2023-01-10 | 富士電機株式会社 | 絶縁ゲート型半導体装置 |
JP7275572B2 (ja) * | 2018-12-27 | 2023-05-18 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP2022082847A (ja) * | 2020-11-24 | 2022-06-03 | 富士電機株式会社 | 炭化珪素半導体装置、半導体パッケージおよび炭化珪素半導体装置の検査方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3746604B2 (ja) * | 1997-12-09 | 2006-02-15 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
JPH08162537A (ja) * | 1994-12-07 | 1996-06-21 | Hitachi Ltd | 半導体装置 |
JP2004055812A (ja) * | 2002-07-19 | 2004-02-19 | Renesas Technology Corp | 半導体装置 |
JP4142029B2 (ja) * | 2004-05-07 | 2008-08-27 | セイコーエプソン株式会社 | 電気光学装置および電子機器 |
JP2006184136A (ja) * | 2004-12-28 | 2006-07-13 | Aitesu:Kk | 半導体解析装置およびその方法 |
WO2009141347A1 (de) * | 2008-05-19 | 2009-11-26 | X-Fab Semiconductor Foundries Ag | Betriebstemperaturmessung eines mos-leistungsbauelements und mos bauelement zur ausfuehrung des verfahrens |
US8017942B2 (en) * | 2008-11-25 | 2011-09-13 | Infineon Technologies Ag | Semiconductor device and method |
JP5486866B2 (ja) * | 2009-07-29 | 2014-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
-
2011
- 2011-05-24 JP JP2011115652A patent/JP5655705B2/ja not_active Expired - Fee Related
-
2012
- 2012-03-19 WO PCT/JP2012/057052 patent/WO2012160868A1/ja active Application Filing
- 2012-05-22 US US13/477,855 patent/US20120298994A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20120298994A1 (en) | 2012-11-29 |
JP2012244102A (ja) | 2012-12-10 |
WO2012160868A1 (ja) | 2012-11-29 |
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