JP2010250920A - 不揮発性半導体メモリ回路 - Google Patents
不揮発性半導体メモリ回路 Download PDFInfo
- Publication number
- JP2010250920A JP2010250920A JP2009175725A JP2009175725A JP2010250920A JP 2010250920 A JP2010250920 A JP 2010250920A JP 2009175725 A JP2009175725 A JP 2009175725A JP 2009175725 A JP2009175725 A JP 2009175725A JP 2010250920 A JP2010250920 A JP 2010250920A
- Authority
- JP
- Japan
- Prior art keywords
- data
- voltage
- level
- input data
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000012795 verification Methods 0.000 claims description 53
- 230000004044 response Effects 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 5
- 239000000872 buffer Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 150000004770 chalcogenides Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012782 phase change material Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1096—Write circuits, e.g. I/O line write drivers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020090032315A KR101038992B1 (ko) | 2009-04-14 | 2009-04-14 | 비휘발성 반도체 메모리 회로 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2010250920A true JP2010250920A (ja) | 2010-11-04 |
| JP2010250920A5 JP2010250920A5 (enExample) | 2012-09-13 |
Family
ID=42934267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009175725A Pending JP2010250920A (ja) | 2009-04-14 | 2009-07-28 | 不揮発性半導体メモリ回路 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8194473B2 (enExample) |
| JP (1) | JP2010250920A (enExample) |
| KR (1) | KR101038992B1 (enExample) |
| TW (1) | TWI420525B (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101080209B1 (ko) * | 2010-09-30 | 2011-11-07 | 주식회사 하이닉스반도체 | 반도체 장치 |
| US8331164B2 (en) * | 2010-12-06 | 2012-12-11 | International Business Machines Corporation | Compact low-power asynchronous resistor-based memory read operation and circuit |
| KR101813175B1 (ko) * | 2011-02-21 | 2017-12-29 | 삼성전자주식회사 | 논리 회로, 상기 논리 회로를 포함하는 집적 회로 및 상기 집적 회로의 동작 방법 |
| KR20130104287A (ko) * | 2012-03-13 | 2013-09-25 | 삼성전자주식회사 | 센싱 검증부를 포함하는 반도체 메모리 장치 |
| KR20140028481A (ko) * | 2012-08-29 | 2014-03-10 | 에스케이하이닉스 주식회사 | 쓰기 전류를 측정할 수 있는 반도체 메모리 장치 및 쓰기 전류 측정 방법 |
| KR102024523B1 (ko) | 2012-12-26 | 2019-09-24 | 삼성전자 주식회사 | 저항체를 이용한 비휘발성 메모리 장치 및 그 구동 방법 |
| KR102079370B1 (ko) | 2013-02-05 | 2020-02-20 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 그것의 쓰기 방법 |
| JP6370444B1 (ja) * | 2017-06-20 | 2018-08-08 | ウィンボンド エレクトロニクス コーポレーション | 半導体記憶装置 |
| US10832765B2 (en) * | 2018-06-29 | 2020-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Variation tolerant read assist circuit for SRAM |
| KR102651128B1 (ko) | 2018-12-11 | 2024-03-26 | 삼성전자주식회사 | 데이터 비교 기록을 수행하는 메모리 장치 및 이를 포함하는 메모리 시스템 |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000076874A (ja) * | 1998-08-27 | 2000-03-14 | Hitachi Ltd | 不揮発性半導体記憶装置 |
| JP2000090675A (ja) * | 1998-09-07 | 2000-03-31 | Hitachi Ltd | 不揮発性半導体メモリおよびそれを内蔵した半導体集積回路 |
| JP2000268593A (ja) * | 1999-03-18 | 2000-09-29 | Matsushita Electric Ind Co Ltd | 不揮発性半導体メモリ |
| JP2004055073A (ja) * | 2002-07-23 | 2004-02-19 | Matsushita Electric Ind Co Ltd | 不揮発性半導体記憶装置および不揮発性半導体記憶装置の検査方法 |
| JP2004234739A (ja) * | 2003-01-29 | 2004-08-19 | Renesas Technology Corp | 不揮発性半導体記憶装置 |
| JP2007133930A (ja) * | 2005-11-08 | 2007-05-31 | Sony Corp | 記憶装置のベリファイ方法 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3344313B2 (ja) * | 1998-03-25 | 2002-11-11 | 日本電気株式会社 | 不揮発性半導体メモリ装置 |
| KR100543442B1 (ko) * | 2002-09-06 | 2006-01-23 | 삼성전자주식회사 | 불 휘발성 반도체 메모리 장치의 메모리 블록들의 쓰기방지 영역을 설정하는 장치 |
| KR100764738B1 (ko) * | 2006-04-06 | 2007-10-09 | 삼성전자주식회사 | 향상된 신뢰성을 갖는 상변화 메모리 장치, 그것의 쓰기방법, 그리고 그것을 포함한 시스템 |
| KR100801082B1 (ko) * | 2006-11-29 | 2008-02-05 | 삼성전자주식회사 | 멀티 레벨 가변 저항 메모리 장치의 구동 방법 및 멀티레벨 가변 저항 메모리 장치 |
| KR100890042B1 (ko) * | 2006-12-29 | 2009-03-25 | 주식회사 하이닉스반도체 | 입력 버퍼 회로 |
| KR101367659B1 (ko) * | 2007-07-12 | 2014-02-25 | 삼성전자주식회사 | 읽기 에러를 줄일 수 있는 멀티 레벨 상 변화 메모리 장치및 그것의 읽기 방법 |
| KR20090016195A (ko) | 2007-08-10 | 2009-02-13 | 주식회사 하이닉스반도체 | 상 변화 메모리 장치 |
| KR100895387B1 (ko) | 2007-10-16 | 2009-04-30 | 주식회사 하이닉스반도체 | 상 변화 메모리 장치 |
| KR20090126587A (ko) * | 2008-06-04 | 2009-12-09 | 삼성전자주식회사 | 상 변화 메모리 장치 및 그것의 읽기 방법 |
-
2009
- 2009-04-14 KR KR1020090032315A patent/KR101038992B1/ko active Active
- 2009-06-30 US US12/494,555 patent/US8194473B2/en active Active
- 2009-07-21 TW TW098124578A patent/TWI420525B/zh active
- 2009-07-28 JP JP2009175725A patent/JP2010250920A/ja active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000076874A (ja) * | 1998-08-27 | 2000-03-14 | Hitachi Ltd | 不揮発性半導体記憶装置 |
| JP2000090675A (ja) * | 1998-09-07 | 2000-03-31 | Hitachi Ltd | 不揮発性半導体メモリおよびそれを内蔵した半導体集積回路 |
| JP2000268593A (ja) * | 1999-03-18 | 2000-09-29 | Matsushita Electric Ind Co Ltd | 不揮発性半導体メモリ |
| JP2004055073A (ja) * | 2002-07-23 | 2004-02-19 | Matsushita Electric Ind Co Ltd | 不揮発性半導体記憶装置および不揮発性半導体記憶装置の検査方法 |
| JP2004234739A (ja) * | 2003-01-29 | 2004-08-19 | Renesas Technology Corp | 不揮発性半導体記憶装置 |
| JP2007133930A (ja) * | 2005-11-08 | 2007-05-31 | Sony Corp | 記憶装置のベリファイ方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US8194473B2 (en) | 2012-06-05 |
| KR20100113804A (ko) | 2010-10-22 |
| TWI420525B (zh) | 2013-12-21 |
| TW201037709A (en) | 2010-10-16 |
| KR101038992B1 (ko) | 2011-06-03 |
| US20100259974A1 (en) | 2010-10-14 |
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| A621 | Written request for application examination |
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| A977 | Report on retrieval |
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