JP2010245160A5 - - Google Patents

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Publication number
JP2010245160A5
JP2010245160A5 JP2009090028A JP2009090028A JP2010245160A5 JP 2010245160 A5 JP2010245160 A5 JP 2010245160A5 JP 2009090028 A JP2009090028 A JP 2009090028A JP 2009090028 A JP2009090028 A JP 2009090028A JP 2010245160 A5 JP2010245160 A5 JP 2010245160A5
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JP
Japan
Prior art keywords
forming
film
region
conductive film
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009090028A
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English (en)
Japanese (ja)
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JP2010245160A (ja
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Publication date
Application filed filed Critical
Priority to JP2009090028A priority Critical patent/JP2010245160A/ja
Priority claimed from JP2009090028A external-priority patent/JP2010245160A/ja
Priority to US12/753,075 priority patent/US8076191B2/en
Publication of JP2010245160A publication Critical patent/JP2010245160A/ja
Priority to US13/304,350 priority patent/US8304820B2/en
Publication of JP2010245160A5 publication Critical patent/JP2010245160A5/ja
Pending legal-status Critical Current

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JP2009090028A 2009-04-02 2009-04-02 半導体装置の製造方法 Pending JP2010245160A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009090028A JP2010245160A (ja) 2009-04-02 2009-04-02 半導体装置の製造方法
US12/753,075 US8076191B2 (en) 2009-04-02 2010-04-01 Method for manufacturing a semiconductor device including memory cell formation region
US13/304,350 US8304820B2 (en) 2009-04-02 2011-11-24 Semiconductor device utilizing dummy gate to enhance processing precision

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009090028A JP2010245160A (ja) 2009-04-02 2009-04-02 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2010245160A JP2010245160A (ja) 2010-10-28
JP2010245160A5 true JP2010245160A5 (cg-RX-API-DMAC7.html) 2012-04-26

Family

ID=42826528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009090028A Pending JP2010245160A (ja) 2009-04-02 2009-04-02 半導体装置の製造方法

Country Status (2)

Country Link
US (2) US8076191B2 (cg-RX-API-DMAC7.html)
JP (1) JP2010245160A (cg-RX-API-DMAC7.html)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101841199B1 (ko) * 2011-12-07 2018-03-23 삼성전자주식회사 반도체 장치의 제조 방법 및 이에 의해 제조된 반도체 장치
US8692306B2 (en) * 2012-01-05 2014-04-08 Taiwan Semiconductor Manufacturing Co., Ltd. Decoupling capacitor and method of making same
JP5964091B2 (ja) * 2012-03-12 2016-08-03 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9917168B2 (en) 2013-06-27 2018-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Metal oxide semiconductor field effect transistor having variable thickness gate dielectric
US9583618B2 (en) * 2013-06-27 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Metal oxide semiconductor field effect transistor having asymmetric lightly doped drain regions
JP2015041674A (ja) * 2013-08-21 2015-03-02 マイクロン テクノロジー， インク． 半導体装置およびその製造方法
JP2015118972A (ja) * 2013-12-17 2015-06-25 シナプティクス・ディスプレイ・デバイス合同会社 半導体装置の製造方法
JP2015118975A (ja) * 2013-12-17 2015-06-25 シナプティクス・ディスプレイ・デバイス合同会社 半導体装置の製造方法
JP2015118974A (ja) * 2013-12-17 2015-06-25 シナプティクス・ディスプレイ・デバイス合同会社 半導体装置の製造方法
US10332882B2 (en) * 2013-12-30 2019-06-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having protective structure over shallow trench isolation region and fabricating method thereof
JP6401974B2 (ja) * 2014-08-27 2018-10-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9425206B2 (en) * 2014-12-23 2016-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Boundary scheme for embedded poly-SiON CMOS or NVM in HKMG CMOS technology
CN105810637B (zh) * 2014-12-31 2019-01-08 上海格易电子有限公司 一种3d nand外围器件的集成方法
US9589976B2 (en) * 2015-04-16 2017-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method to reduce polysilicon loss from flash memory devices during replacement gate (RPG) process in integrated circuits
TWI672766B (zh) * 2015-08-10 2019-09-21 聯華電子股份有限公司 隔離元件及其製作方法
JP6560933B2 (ja) * 2015-08-25 2019-08-14 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US10535670B2 (en) * 2016-02-25 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Non-volatile memory having an erase gate formed between two floating gates with two word lines formed on other sides and a method for forming the same
JP2018056238A (ja) 2016-09-27 2018-04-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP7038559B2 (ja) * 2018-02-05 2022-03-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US10644013B2 (en) * 2018-08-15 2020-05-05 Taiwan Semiconductor Manufacturing Co., Ltd. Cell boundary structure for embedded memory
CN116801622B (zh) * 2018-09-11 2024-11-15 长鑫存储技术有限公司 半导体器件及其制备方法
US10804281B2 (en) * 2018-09-28 2020-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Anti-dishing structure for embedded memory
JP2023180086A (ja) * 2022-06-08 2023-12-20 キオクシア株式会社 半導体記憶装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2867975B2 (ja) * 1996-10-08 1999-03-10 日本電気株式会社 レジストパターンの形成方法
JP4558557B2 (ja) * 2005-03-31 2010-10-06 富士通セミコンダクター株式会社 不揮発性半導体記憶装置
JP4992722B2 (ja) * 2005-12-14 2012-08-08 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2007234861A (ja) * 2006-03-01 2007-09-13 Renesas Technology Corp 半導体装置の製造方法
JP2008140977A (ja) * 2006-12-01 2008-06-19 Renesas Technology Corp 半導体装置の製造方法
KR100944591B1 (ko) * 2007-12-03 2010-02-25 주식회사 동부하이텍 반도체 소자 및 그 제조 방법

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