JP2010141272A - エピタキシャルウェーハとその製造方法 - Google Patents

エピタキシャルウェーハとその製造方法 Download PDF

Info

Publication number
JP2010141272A
JP2010141272A JP2008318897A JP2008318897A JP2010141272A JP 2010141272 A JP2010141272 A JP 2010141272A JP 2008318897 A JP2008318897 A JP 2008318897A JP 2008318897 A JP2008318897 A JP 2008318897A JP 2010141272 A JP2010141272 A JP 2010141272A
Authority
JP
Japan
Prior art keywords
epitaxial
oxygen concentration
silicon
epitaxial wafer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008318897A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010141272A5 (enExample
Inventor
Toshiaki Ono
敏昭 小野
Yumi Hoshino
由美 星野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Corp
Original Assignee
Sumco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corp filed Critical Sumco Corp
Priority to JP2008318897A priority Critical patent/JP2010141272A/ja
Priority to US12/634,899 priority patent/US9362114B2/en
Publication of JP2010141272A publication Critical patent/JP2010141272A/ja
Publication of JP2010141272A5 publication Critical patent/JP2010141272A5/ja
Priority to US15/138,526 priority patent/US9991386B2/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/796—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Vapour Deposition (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2008318897A 2008-12-15 2008-12-15 エピタキシャルウェーハとその製造方法 Pending JP2010141272A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008318897A JP2010141272A (ja) 2008-12-15 2008-12-15 エピタキシャルウェーハとその製造方法
US12/634,899 US9362114B2 (en) 2008-12-15 2009-12-10 Epitaxial wafer and method of manufacturing the same
US15/138,526 US9991386B2 (en) 2008-12-15 2016-04-26 Epitaxial wafer and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008318897A JP2010141272A (ja) 2008-12-15 2008-12-15 エピタキシャルウェーハとその製造方法

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2012277377A Division JP5516713B2 (ja) 2012-12-19 2012-12-19 エピタキシャルウェーハの製造方法
JP2012277376A Division JP5704155B2 (ja) 2012-12-19 2012-12-19 エピタキシャルウェーハの製造方法

Publications (2)

Publication Number Publication Date
JP2010141272A true JP2010141272A (ja) 2010-06-24
JP2010141272A5 JP2010141272A5 (enExample) 2012-02-16

Family

ID=42241050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008318897A Pending JP2010141272A (ja) 2008-12-15 2008-12-15 エピタキシャルウェーハとその製造方法

Country Status (2)

Country Link
US (2) US9362114B2 (enExample)
JP (1) JP2010141272A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015129133A1 (ja) * 2014-02-26 2015-09-03 株式会社Sumco エピタキシャルシリコンウェーハの製造方法及びエピタキシャルシリコンウェーハ
JP2015216371A (ja) * 2014-05-09 2015-12-03 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ 半導体デバイスを形成するための方法および半導体デバイス

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7998867B2 (en) * 2007-11-08 2011-08-16 Sumco Corporation Method for manufacturing epitaxial wafer
WO2009060914A1 (ja) * 2007-11-08 2009-05-14 Sumco Corporation エピタキシャルウェーハ
JP2011082443A (ja) * 2009-10-09 2011-04-21 Sumco Corp エピタキシャルウェーハおよびその製造方法
TWI541864B (zh) 2012-12-06 2016-07-11 世創電子材料公司 磊晶晶圓及其製造方法
JP6610056B2 (ja) 2015-07-28 2019-11-27 株式会社Ｓｕｍｃｏ エピタキシャルシリコンウェーハの製造方法
CN106571296A (zh) * 2015-10-13 2017-04-19 上海新昇半导体科技有限公司 晶圆的形成方法
CN106591944B (zh) * 2015-10-15 2018-08-24 上海新昇半导体科技有限公司 单晶硅锭及晶圆的形成方法
US10026843B2 (en) * 2015-11-30 2018-07-17 Taiwan Semiconductor Manufacturing Co., Ltd. Fin structure of semiconductor device, manufacturing method thereof, and manufacturing method of active region of semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03133121A (ja) * 1989-10-19 1991-06-06 Showa Denko Kk 半導体デバイス用シリコン基板及びその製造方法
JP2002217413A (ja) * 2001-01-19 2002-08-02 Univ Nagoya 半導体装置製造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4659400A (en) * 1985-06-27 1987-04-21 General Instrument Corp. Method for forming high yield epitaxial wafers
US5221413A (en) 1991-04-24 1993-06-22 At&T Bell Laboratories Method for making low defect density semiconductor heterostructure and devices made thereby
JPH05326467A (ja) 1992-05-15 1993-12-10 Toshiba Corp 半導体基板及びその製造方法
US6284384B1 (en) * 1998-12-09 2001-09-04 Memc Electronic Materials, Inc. Epitaxial silicon wafer with intrinsic gettering
JP3884203B2 (ja) 1998-12-24 2007-02-21 株式会社東芝 半導体装置の製造方法
JP3988307B2 (ja) 1999-03-26 2007-10-10 株式会社Ｓｕｍｃｏ シリコン単結晶、シリコンウェーハ及びエピタキシャルウェーハ
JP4269541B2 (ja) 2000-08-01 2009-05-27 株式会社Ｓｕｍｃｏ 半導体基板と電界効果型トランジスタ並びにＳｉＧｅ層の形成方法及びこれを用いた歪みＳｉ層の形成方法と電界効果型トランジスタの製造方法
US6514886B1 (en) * 2000-09-22 2003-02-04 Newport Fab, Llc Method for elimination of contaminants prior to epitaxy
JP4506035B2 (ja) 2001-05-31 2010-07-21 株式会社Sumco 半導体基板と電界効果型トランジスタ並びにＳｉＧｅ層の形成方法及びこれを用いた歪みＳｉ層の形成方法と電界効果型トランジスタの製造方法
JP2004111722A (ja) * 2002-09-19 2004-04-08 Toshiba Corp 半導体装置
US6995079B2 (en) * 2003-08-29 2006-02-07 Semiconductor Energy Laboratory Co., Ltd. Ion implantation method and method for manufacturing semiconductor device
JP4711167B2 (ja) 2004-08-25 2011-06-29 信越半導体株式会社 シリコンエピタキシャルウェーハの製造方法
US7691714B2 (en) * 2005-01-25 2010-04-06 Texas Instruments Incorporated Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor
JP4654710B2 (ja) 2005-02-24 2011-03-23 信越半導体株式会社 半導体ウェーハの製造方法
US7323392B2 (en) * 2006-03-28 2008-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. High performance transistor with a highly stressed channel
KR20080102065A (ko) * 2007-05-18 2008-11-24 삼성전자주식회사 에피택시얼 실리콘 구조물 형성 방법 및 이를 이용한 반도체 소자의 형성 방법
JP4550870B2 (ja) * 2007-07-23 2010-09-22 株式会社東芝 半導体装置の製造方法
JP5012554B2 (ja) 2008-02-19 2012-08-29 株式会社Ｓｕｍｃｏ エピタキシャルウェーハの製造方法
JP2010016312A (ja) 2008-07-07 2010-01-21 Sumco Corp エピタキシャルウェーハの製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03133121A (ja) * 1989-10-19 1991-06-06 Showa Denko Kk 半導体デバイス用シリコン基板及びその製造方法
JP2002217413A (ja) * 2001-01-19 2002-08-02 Univ Nagoya 半導体装置製造方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015129133A1 (ja) * 2014-02-26 2015-09-03 株式会社Sumco エピタキシャルシリコンウェーハの製造方法及びエピタキシャルシリコンウェーハ
JP2015162522A (ja) * 2014-02-26 2015-09-07 株式会社Sumco エピタキシャルシリコンウェーハの製造方法及びエピタキシャルシリコンウェーハ
KR20160122802A (ko) 2014-02-26 2016-10-24 가부시키가이샤 사무코 에피택셜 실리콘 웨이퍼의 제조방법 및 에피택셜 실리콘 웨이퍼
US9818609B2 (en) 2014-02-26 2017-11-14 Sumco Corporation Epitaxial-silicon-wafer manufacturing method and epitaxial silicon wafer
KR101925515B1 (ko) * 2014-02-26 2018-12-06 가부시키가이샤 사무코 에피택셜 실리콘 웨이퍼의 제조방법 및 에피택셜 실리콘 웨이퍼
DE112014006413B4 (de) 2014-02-26 2020-06-04 Sumco Corporation Herstellungsverfahren für epitaktischen Siliciumwafer
JP2015216371A (ja) * 2014-05-09 2015-12-03 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ 半導体デバイスを形成するための方法および半導体デバイス
US9847229B2 (en) 2014-05-09 2017-12-19 Infineon Technologies Ag Method for forming a semiconductor device and semiconductor device

Also Published As

Publication number Publication date
US9362114B2 (en) 2016-06-07
US20160240677A1 (en) 2016-08-18
US9991386B2 (en) 2018-06-05
US20100151692A1 (en) 2010-06-17

Similar Documents

Publication Publication Date Title
JP2010141272A (ja) エピタキシャルウェーハとその製造方法
JP6156188B2 (ja) エピタキシャルシリコンウェーハの製造方法
JP2003124219A (ja) シリコンウエーハおよびエピタキシャルシリコンウエーハ
EP2187429B1 (en) Bonding wafer manufacturing method
JP7342392B2 (ja) エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ
JP5704155B2 (ja) エピタキシャルウェーハの製造方法
JP4700324B2 (ja) 半導体基板の製造方法
US11888036B2 (en) Method for setting a nitrogen concentration of a silicon epitaxial film in manufacturing an epitaxial silicon wafer
JP5463693B2 (ja) シリコンエピタキシャルウェーハの製造方法
JP5516713B2 (ja) エピタキシャルウェーハの製造方法
JP4972330B2 (ja) シリコンエピタキシャルウェーハの製造方法
JP2012204369A (ja) エピタキシャルウェーハの製造方法
JP2005079134A (ja) 半導体基板およびその製造方法
JP4590876B2 (ja) エピタキシャルシリコンウェーハの製造方法及びその方法で製造されたシリコンウェーハ
US20150187597A1 (en) Method to improve slip resistance of silicon wafers
JP2010098284A (ja) エピタキシャル基板用シリコンウェハの製造方法及びエピタキシャル基板の製造方法
EP1675166A2 (en) Internally gettered heteroepitaxial semiconductor wafers and methods of manufacturing such wafers
JP2008159976A (ja) シリコンエピタキシャルウェーハ及びその製造方法、並びに半導体デバイスの製造方法及びｓｏｉウェーハの製造方法
EP2172967A1 (en) Method for manufacturing silicon carbide
KR20230065995A (ko) Soi 웨이퍼의 제조방법 및 soi 웨이퍼

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111214

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20111214

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111216

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20121012

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121023

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20130319