JP2010135737A - 半導体装置 - Google Patents
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Abstract
【解決手段】本発明の半導体装置11は、リードフレーム13のチップマウント部13a上に半導体チップ12をマウントし、全体を樹脂15でモールドして構成されたものにおいて、リードフレーム13の複数のリード部13c〜13g上に縦置きで搭載され上下両端に電極部を有する複数のチップ部品14を備えると共に、複数のチップ部品14の各上端部に搭載されグランド電位に接続された導電性プレート17を備えたものである。
【選択図】図1
Description
Claims (19)
- リードフレームのチップマウント部上に半導体チップをマウントし、全体を樹脂でモールドして構成された半導体装置において、
前記チップマウント部上に搭載され、両端に電極部を有する複数のチップ部品と、
前記複数のチップ部品の各他方の電極部と前記リードフレームの複数のリード部との各間にボンディングされたワイヤとを備えたことを特徴とする半導体装置。 - 前記複数のチップ部品を搭載する基板を備え、
前記基板を前記チップマウント部上に搭載したことを特徴とする請求項1記載の半導体装置。 - リードフレームのチップマウント部上に半導体チップをマウントし、全体を樹脂でモールドして構成された半導体装置において、
前記リードフレームの複数のリード部上に横置きで搭載され、両端に電極部を有する複数のチップ部品を備え、
前記複数のチップ部品の各一方の電極と前記複数のリード部との間は導電性接着剤で接着し、前記複数のチップ部品の各他方の電極と前記複数のリード部との間は絶縁性接着剤で接着し、
前記複数のチップ部品の各他方の電極部にボンディングされたワイヤを備えたことを特徴とする半導体装置。 - 前記ワイヤは、グランド電位に接続されていることを特徴とする請求項11記載の半導体装置。
- 前記チップ部品の上に1個以上のチップ部品を積み重ねると共に、これら積み重ねたチップ部品を直列接続するように構成したことを特徴とする請求項3または4に記載の半導体装置。
- リードフレームのチップマウント部上に半導体チップをマウントし、全体を樹脂でモールドして構成された半導体装置において、
前記リードフレームの複数のリード部上に横置きで搭載され、両端に電極部を有する複数のチップ部品と、
前記複数のチップ部品の上に搭載された導電性プレートとを備え、
前記複数のチップ部品の各一方の電極と前記複数のリード部との間は導電性接着剤で接着し、前記複数のチップ部品の各他方の電極と前記複数のリード部との間は絶縁性接着剤で接着し、前記複数のチップ部品の各一方の電極と前記導電性プレートとの間は絶縁性接着剤で接着し、前記複数のチップ部品の各他方の電極と前記導電性プレートとの間は導電性接着剤で接着するように構成したことを特徴とする半導体装置。 - 前記導電性プレートは、グランド電位に接続されていることを特徴とする請求項6記載の半導体装置。
- リードフレームのチップマウント部上に半導体チップをマウントし、全体を樹脂でモールドして構成された半導体装置において、
前記リードフレームの複数のリード部上に縦置きで搭載され、上下両端に電極部を有する複数のチップ部品と、
前記複数のチップ部品の各上端部に搭載された導電性プレートとを備えたことを特徴とする半導体装置。 - 前記導電性プレートには、前記チップ部品の上下方向の長さ寸法の長短に対応するように凸部または凹部が折曲形成されていることを特徴とする請求項8記載の半導体装置。
- 前記導電性プレートにおける前記チップ部品が搭載される部分の近傍部位に、溝部が形成されていることを特徴とする請求項8または9記載の半導体装置。
- 前記導電性プレートまたは前記リード部には、前記チップ部品の下端部または上端部が嵌合する嵌合凹部が形成されていることを特徴とする請求項8記載の半導体装置。
- 前記複数のチップ部品を予め樹脂でモールドすると共に、前記チップ部品の電極部の端面を露出させておくように構成したことを特徴とする請求項8記載の半導体装置。
- 前記導電性プレートは、グランド電位に接続されていることを特徴とする請求項8記載の半導体装置。
- リードフレームのチップマウント部上に半導体チップをマウントし、全体を樹脂でモールドして構成された半導体装置において、
前記リードフレームの複数のリード部上に縦置きで搭載され、上下両端に電極部を有する複数のチップ部品と、
前記複数のチップ部品の各上端部の電極部にボンディングされたワイヤとを備えたことを特徴とする半導体装置。 - 前記ワイヤは、グランド電位に接続されていることを特徴とする請求項14記載の半導体装置。
- リードフレームのチップマウント部上に半導体チップをマウントし、全体を樹脂でモールドして構成された半導体装置において、
前記リードフレームの複数のリード部上に縦置きで搭載され、上下両端に電極部を有する複数のチップ部品を備え、
全体を樹脂でモールドしたときに、前記複数のチップ部品の各上端部の電極部を露出させるように構成したことを特徴とする半導体装置。 - リードフレームのチップマウント部上に半導体チップをマウントし、全体を樹脂でモールドして構成された半導体装置において、
前記リードフレームの複数のリード部上に縦置きで搭載され、上下両端に電極部を有する複数のチップ部品と、
前記チップマウント部に前記チップ部品が搭載されているリード部に近接するように設けられたリード部とを備え、
前記チップマウント部に設けられたリード部を変形させてその先端部を前記複数のチップ部品の各上端部の電極部に搭載するように構成したことを特徴とする半導体装置。 - 前記チップマウント部に設けられたリード部は、グランド電位に接続されていることを特徴とする請求項17記載の半導体装置。
- リードフレームのチップマウント部上に半導体チップをマウントし、全体を樹脂でモールドして構成された半導体装置において、
前記リードフレームの複数のリード部上に縦置きで搭載され、上下両端に電極部を有する複数のチップ部品を備え、
前記リードフレームのチップマウント部とリード部を別体とし、
前記チップマウント部の端部を前記複数のチップ部品の各上端部の電極部に搭載するように構成したことを特徴とする半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009163662A JP4883145B2 (ja) | 2008-10-30 | 2009-07-10 | 半導体装置 |
US12/588,739 US8624367B2 (en) | 2008-10-30 | 2009-10-27 | Semiconductor device including semiconductor chip mounted on lead frame |
CN200910207690A CN101728372A (zh) | 2008-10-30 | 2009-10-29 | 包含安装在引线框上的半导体芯片的半导体装置 |
CN2013100632308A CN103199074A (zh) | 2008-10-30 | 2009-10-29 | 包含安装在引线框上的半导体芯片的半导体装置 |
US14/091,507 US9029993B2 (en) | 2008-10-30 | 2013-11-27 | Semiconductor device including semiconductor chip mounted on lead frame |
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Application Number | Priority Date | Filing Date | Title |
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JP2008279791 | 2008-10-30 | ||
JP2008279791 | 2008-10-30 | ||
JP2009163662A JP4883145B2 (ja) | 2008-10-30 | 2009-07-10 | 半導体装置 |
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JP2011224008A Division JP5299492B2 (ja) | 2008-10-30 | 2011-10-11 | 半導体装置 |
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JP2010135737A true JP2010135737A (ja) | 2010-06-17 |
JP4883145B2 JP4883145B2 (ja) | 2012-02-22 |
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JP2009163662A Expired - Fee Related JP4883145B2 (ja) | 2008-10-30 | 2009-07-10 | 半導体装置 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012104633A (ja) * | 2010-11-10 | 2012-05-31 | Mitsubishi Electric Corp | 半導体装置 |
JP2019021944A (ja) * | 2018-11-07 | 2019-02-07 | ラピスセミコンダクタ株式会社 | 半導体装置および計測装置 |
JP2021190522A (ja) * | 2020-05-28 | 2021-12-13 | 三菱電機株式会社 | 半導体装置 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102011118932A1 (de) | 2011-11-21 | 2013-05-23 | Micronas Gmbh | Vorrichtung mit einem integrierten Schaltkreis |
JP6094592B2 (ja) * | 2012-10-01 | 2017-03-15 | 富士電機株式会社 | 半導体装置とその製造方法 |
CN103762213B (zh) * | 2014-01-24 | 2016-08-24 | 矽力杰半导体技术(杭州)有限公司 | 应用于开关型调节器的集成电路组件 |
US10181410B2 (en) | 2015-02-27 | 2019-01-15 | Qualcomm Incorporated | Integrated circuit package comprising surface capacitor and ground plane |
DE102018124695A1 (de) * | 2017-11-15 | 2019-05-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrieren von Passivvorrichtungen in Package-Strukturen |
JP7211267B2 (ja) * | 2019-05-29 | 2023-01-24 | 株式会社デンソー | 半導体パッケージの製造方法 |
CN110600455A (zh) * | 2019-09-25 | 2019-12-20 | 江苏盐芯微电子有限公司 | 一种内置电容的ic芯片及封装方法 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62260343A (ja) * | 1986-05-06 | 1987-11-12 | Mitsubishi Electric Corp | 半導体装置 |
JPH027459A (ja) * | 1988-06-24 | 1990-01-11 | Nec Corp | 半導体パッケージ |
JPH08250646A (ja) * | 1995-03-10 | 1996-09-27 | Shindengen Electric Mfg Co Ltd | 混成集積回路装置 |
JP2003188198A (ja) * | 2001-12-20 | 2003-07-04 | Matsushita Electric Ind Co Ltd | 電子部品実装済み部品の製造方法及び製造装置 |
JP2004228402A (ja) * | 2003-01-24 | 2004-08-12 | Mitsubishi Electric Corp | 半導体装置 |
JP2006032470A (ja) * | 2004-07-13 | 2006-02-02 | Denso Corp | 電子装置 |
JP2006245618A (ja) * | 2006-06-14 | 2006-09-14 | Fujitsu Ltd | 受動素子内蔵半導体装置 |
JP2007012857A (ja) * | 2005-06-30 | 2007-01-18 | Renesas Technology Corp | 半導体装置 |
JP2007157801A (ja) * | 2005-12-01 | 2007-06-21 | Matsushita Electric Ind Co Ltd | 半導体モジュールとその製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0181896B1 (ko) * | 1996-09-14 | 1999-05-15 | 삼성전자주식회사 | 고속 광 모듈의 광대역화 장치 |
WO1999034444A1 (fr) | 1997-12-25 | 1999-07-08 | Mitsubishi Denki Kabushiki Kaisha | Dispositif a semiconducteur et son procede de fabrication |
JP2000058740A (ja) | 1998-07-31 | 2000-02-25 | Kankyo Denji Gijutsu Kenkyusho:Kk | コモンモードフィルタ素子内蔵半導体デバイス |
JP3312246B2 (ja) | 1999-06-18 | 2002-08-05 | 松尾電機株式会社 | チップコンデンサの製造方法 |
JP2003017650A (ja) | 2001-06-28 | 2003-01-17 | Sony Corp | 半導体集積回路 |
JP2005236171A (ja) | 2004-02-23 | 2005-09-02 | Matsushita Electric Ind Co Ltd | 固体電解コンデンサ及びその製造方法 |
TWI226119B (en) * | 2004-03-11 | 2005-01-01 | Advanced Semiconductor Eng | Semiconductor package |
US7161797B2 (en) * | 2005-05-17 | 2007-01-09 | Vishay Sprague, Inc. | Surface mount capacitor and method of making same |
JP4814639B2 (ja) * | 2006-01-24 | 2011-11-16 | 富士通セミコンダクター株式会社 | 半導体装置および半導体装置の製造方法 |
US7948078B2 (en) * | 2006-07-25 | 2011-05-24 | Rohm Co., Ltd. | Semiconductor device |
-
2009
- 2009-07-10 JP JP2009163662A patent/JP4883145B2/ja not_active Expired - Fee Related
- 2009-10-27 US US12/588,739 patent/US8624367B2/en not_active Expired - Fee Related
- 2009-10-29 CN CN2013100632308A patent/CN103199074A/zh active Pending
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-
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- 2013-11-27 US US14/091,507 patent/US9029993B2/en not_active Expired - Fee Related
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62260343A (ja) * | 1986-05-06 | 1987-11-12 | Mitsubishi Electric Corp | 半導体装置 |
JPH027459A (ja) * | 1988-06-24 | 1990-01-11 | Nec Corp | 半導体パッケージ |
JPH08250646A (ja) * | 1995-03-10 | 1996-09-27 | Shindengen Electric Mfg Co Ltd | 混成集積回路装置 |
JP2003188198A (ja) * | 2001-12-20 | 2003-07-04 | Matsushita Electric Ind Co Ltd | 電子部品実装済み部品の製造方法及び製造装置 |
JP2004228402A (ja) * | 2003-01-24 | 2004-08-12 | Mitsubishi Electric Corp | 半導体装置 |
JP2006032470A (ja) * | 2004-07-13 | 2006-02-02 | Denso Corp | 電子装置 |
JP2007012857A (ja) * | 2005-06-30 | 2007-01-18 | Renesas Technology Corp | 半導体装置 |
JP2007157801A (ja) * | 2005-12-01 | 2007-06-21 | Matsushita Electric Ind Co Ltd | 半導体モジュールとその製造方法 |
JP2006245618A (ja) * | 2006-06-14 | 2006-09-14 | Fujitsu Ltd | 受動素子内蔵半導体装置 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012104633A (ja) * | 2010-11-10 | 2012-05-31 | Mitsubishi Electric Corp | 半導体装置 |
JP2019021944A (ja) * | 2018-11-07 | 2019-02-07 | ラピスセミコンダクタ株式会社 | 半導体装置および計測装置 |
JP2021190522A (ja) * | 2020-05-28 | 2021-12-13 | 三菱電機株式会社 | 半導体装置 |
JP7308793B2 (ja) | 2020-05-28 | 2023-07-14 | 三菱電機株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
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US8624367B2 (en) | 2014-01-07 |
US20140084437A1 (en) | 2014-03-27 |
JP4883145B2 (ja) | 2012-02-22 |
US9029993B2 (en) | 2015-05-12 |
CN101728372A (zh) | 2010-06-09 |
US20100109136A1 (en) | 2010-05-06 |
CN103199074A (zh) | 2013-07-10 |
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