JP2010086983A - リードフレーム型基板の製造方法と半導体装置 - Google Patents
リードフレーム型基板の製造方法と半導体装置 Download PDFInfo
- Publication number
- JP2010086983A JP2010086983A JP2008250860A JP2008250860A JP2010086983A JP 2010086983 A JP2010086983 A JP 2010086983A JP 2008250860 A JP2008250860 A JP 2008250860A JP 2008250860 A JP2008250860 A JP 2008250860A JP 2010086983 A JP2010086983 A JP 2010086983A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- resin
- frame type
- type substrate
- connection post
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229920005989 resin Polymers 0.000 claims abstract description 48
- 239000011347 resin Substances 0.000 claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 24
- 238000000465 moulding Methods 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 16
- 229910052802 copper Inorganic materials 0.000 description 16
- 239000010949 copper Substances 0.000 description 16
- 238000007747 plating Methods 0.000 description 13
- 239000010410 layer Substances 0.000 description 10
- 239000000243 solution Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 238000003825 pressing Methods 0.000 description 4
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 3
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000005484 gravity Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01067—Holmium [Ho]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Die Bonding (AREA)
Abstract
【解決手段】イ)金属板の第1と第2の面に感光性レジストをコート又はドライフィルムを貼付し、ロ)パターン露光と現像により接続用ポストと配線パターンを形成する各レジストパターンを設け、ハ)第1面を中途エッチングし接続用ポストを形成し、ニ)その面が埋没するまでプリモールド用樹脂を充填し、ホ)接続用ポスト底面が露出する迄プリモールド用樹脂を均一に除去し、ヘ)第2面のエッチングにより配線パターンを形成する。
【選択図】図1
Description
このインターポーザの一方の面に、半導体素子を実装し、他方の面もしくは基板の周辺でプリント基板との接続がとられる。インターポーザは内部もしくは表面に金属リードフレームを有しており、リードフレームにより電気的接続経路を引き回して、プリント基板との接続を行う外部接続端子のピッチを拡張している。
図2(a)に示すように、アルミニウムあるいは銅からなるリードフレームの中央部に半導体素子22を搭載する平坦部分21を設け、外周部にピッチの広いリード23を配設したもので、リード23と半導体素子の電気的接続用端子との接続には、金線などのメタルワイヤー24によるボンディング法を使用したものである。図2(b)に示すように、最終的には全体を樹脂でモールド25して一体化する。
しかし、図2のインターポーザでは、電気的接続が半導体素子の外周部とリードフレームの外周部とでしか行えないため、端子数が多い半導体素子には不向きといえる。
面積が狭く端子数が多い半導体素子の場合には、半導体素子の接続端子は、半導体素子の底面にアレイ状に配置して形成されることが多い。そのため、インターポーザ側の外部接続端子も同一なアレイ状の配置として、インターポーザとプリント基板との接続には微少な半田ボールを用いるフリップチップ接続方式が採用される。インターポーザ内の配線は、上部から垂直方向にドリルもしくはレーザーで窄孔し、孔内に金属めっきを行うことにより、上下の電気的銅通がとられる。
しかし、この方式によるインターポーザでは、外部接続端子のピッチは150〜200μm程度まで微細化できるため、接続端子数を増やすことはできるが、接合の信頼性や安定性は低下し、高い信頼性が要求される車載用などには向いていない。
いずれの場合であっても、半導体素子の小型化、多ピン化、高速化に対応して、インターポーザの半導体素子のとの接続部分のファインピッチ化及び高速信号対応が進んでいる。微細化の進展を考慮すると、端子部分のピッチは80〜100μmが必要である。
この点について、図2を用いて説明する。
しかし、最終的には、保持材27は不要であるため、モールド加工をした後に、取り外して棄てることになり、コストアップに繋がる。
この一対策は、リードフレーム型基板を製造するうえで、金属板の第1の面には接続用ポスト形成用のレジストパターン、第2の面には配線パターン形成用のレジストパターンを形成し、第1の面の上から銅を所望の厚さまでエッチングしたのち、第1の面にプリモールド用樹脂を塗布しプリモールド層を形成し、その後に、第2の面のエッチングを行い配線を形成して、その後に両面のレジストを剥離するということになる。
即ち、上記の一対策において、金属板の厚さ方向途中までエッチングした面にプリモールド樹脂を塗布する工程は技術的に困難である。塗付の厚さは、リードフレームに必要な剛性を与えるのに十分な程度必要であり、なおかつ、接続用ポストの底面は、完全に露出していなければならない。
また、表面張力のために、樹脂が球状になって、狭い範囲にとどまる場合もあり、その場合は注入した樹脂が少量であっても、高さが大きくなり、接続用ポストの底面に達してしまう不良も発生しやすいと云う問題も心配される。
それから、ディスペンサー等の装置を用いて、塗付面底に複数の注入箇所を設定することも考えられるが、やはりプリモールド樹脂の粘性のために、ある注入箇所から他の箇所に移動する間に、樹脂が糸をひき、それが接続用ポストの底面に付着するという不良も発生しやすいと云う問題も心配される。
(ロ)前記第1の面と第2の面に、前記感光性レジストまたは前記ドライフィルムにパターン露光を行った後に現像することで、該第1の面には接続用ポスト形成用のレジストパターンを、又、該第2の面には配線パターン形成用のレジストパターンを形成し、
(ハ)前記第1の面の側を、前記金属板の中途までエッチングを行い、前記接続用ポストを形成し、
(ニ)前記第1の面の側に、プリモールド用の樹脂を、該エッチングが成された面が埋没する厚さまで充填し、
(ホ)前記プリモールド用の樹脂を、前記接続用ポストの底面が露出するまで、厚さ方向に均一に除去し、
(ヘ)その後、前記第2の面の側をエッチングすることで配線パターンを形成する、
以上を経ることを特徴とするリードフレーム型基板の製造方法である。
これにより、プリモールド樹脂の上面の高さは、接続用ポストの底面とほぼ同じ高さとなり、リードフレーム型基板の剛性を保ち、なおかつ接続用ポスト底面が完全に露出するという目標を、確実に達成することができる。
これにより、液状樹脂を用いるよりも、簡便に所望のリードフレーム型基板を製造することができる。
これにより、プリモールド樹脂を充填する際の、気泡等の発生を低減することができ、より高品質なリードフレーム型基板を製造することができる。
プリモールド樹脂のこの高さは、リードフレーム型基板の支持体として、十分な剛性をもち、なおかつ、接続用ポストが、完全に露出するという条件を兼ね備えている。そのため、十分な機械的強度をもち、なおかつ接続においても高い信頼性をもつ接合強度を得られる。
製造した個々の単位のLGAのサイズは10mm角で、168ピンの平面視でアレイ状の外部接続部をもつもので、基板に多面付けして、以下の製造工程を経た後に切断、断裁を行い、個々のLGAタイプのリードフレーム型基板を得た。
次いで、図1(b)に示すように、銅基板1の両面ロールコーターで感光性レジスト2(東京応化(株)製、OFPR4000)を5μmの厚さになるようにコーティングした後、90℃でプリベークをした。
次に、所望のパターンを有するパターン露光用フォトマスクを介して、両面からパターン露光し、その後1%水酸化ナトリウム溶液で現像処理を行った後に、水洗およびポストベークを行い、図1(c)に示すようにレジストパターン3を得た。なお、銅基板の一方の面側(半導体素子が搭載される面とは反対側の面であり、本実施例では以下、第1の面側と記す)には、接続用ポストを形成するためのレジストパターンを形成し、他方の面側(半導体素子が搭載される面であり、本実施例では以下、第2の面側と記す)には、配線パターンを形成するためのレジストパターンを形成した。
この他、半導体素子10の周囲のランド4のうち幾つかを、半導体素子の下面に位置する接続用ポスト5に電気的に接続させる必要がある。そのため、半導体素子10周辺のランド4の幾つかと各々接続した配線パターン6を半導体素子下面に位置する接続用ポスト5と接続するよう基板の外周から中心方向に向けて、例えば、放射状に、形成している(図示せず)。
塩化第二鉄溶液の比重は1.38、液温50℃とした。第1回目のエッチングの際、接続用ポスト形成用のレジストパターンが形成された部位の銅基板には、エッチング処理が行われない。そのため、銅基板の厚み方向に、第1回目のエッチング処理で形成されたエッチング面から銅基板下側面までの高さを有して延在する、プリント基板との外部接続を可能とした接続用ポストを形成することが出来る。
なお、第1回目のエッチングでは、エッチング処理を行う部位の銅基板をエッチング処理で完全に溶解除去するものではなく、所定の厚さの銅基板となった段階でエッチング処理を終了するよう、中途までエッチング処理を行う。
次に、第1の面に関して、20%水酸化ナトリウム水溶液によって、レジストの剥離を行った、剥離液の温度は100℃とた。
プレスに際しては、真空加圧式ラミネート装置を用い、プレス部の温度は100℃、真空チャンバー内の真空度は0.2torr、プレス時間は30秒にてフィルム樹脂のプレス加工を行った。
また、真空チャンバー内でのプレス加工を行うことは、樹脂内に生じた空隙を解消する効果があり、樹脂内のボイドの発生を抑えることができる。
その後に、図1(g)に示すように、第1の面を覆っている樹脂を、接続用ポストの底面が露出するまで研磨除去した。装置としては、バフロール回転式研磨装置を用い、バフロールの番手は、800番相当を使用した。
次いで、図1(h)に示すように、第2の面のレジストパターンの剥離を行い、所望のリードフレーム型LGA基板を得た。
次いで、面付けされた半導体基板に断裁を行い、個々の半導体基板を得た。
2 感光性レジスト
3 レジストパターン
4 ワイヤボンディング用ランド
5 接続用ポスト
6 配線パターン
7 下面
11 プリモールド層
12 めっき層
13 固定用接着剤
21 リードフレーム(平坦部)
10、22 半導体素子
23 リード
24 メタルワイヤー
25 モールド用樹脂
26 取り出し電極
27 保持材
Claims (5)
- (イ)金属板の第1の面と第2の面に、感光性レジストをコートするか、又はドライフィルムを貼付するかのいずれかを行い、
(ロ)前記第1の面と第2の面に、前記感光性レジストまたは前記ドライフィルムにパターン露光を行った後に現像することで、該第1の面には接続用ポスト形成用のレジストパターンを、又、該第2の面には配線パターン形成用のレジストパターンを形成し、
(ハ)前記第1の面の側を、前記金属板の中途までエッチングを行い、前記接続用ポストを形成し、
(ニ)前記第1の面の側に、プリモールド用の樹脂を、該エッチングが成された面が埋没する厚さまで充填し、
(ホ)前記プリモールド用の樹脂を、前記接続用ポストの底面が露出するまで、厚さ方向に均一に除去し、
(ヘ)その後、前記第2の面の側をエッチングすることで配線パターンを形成する、
以上を経ることを特徴とするリードフレーム型基板の製造方法。 - 前記プリモールド用の樹脂がフィルムタイプであること、を特徴とする請求項1に記載のリードフレーム型基板の製造方法。
- 前記プリモールド用の樹脂を充填する場合に、真空チャンバー内で該充填を行うこと、を特徴とする請求項1又は2のいずれかに記載のリードフレーム型基板の製造方法。
- 請求項1乃至3のいずれかに記載のリードフレーム型基板の製造方法によって得られた該リードフレーム型基板に、半導体が実装されており、該リードフレーム型基板と該半導体素子とがワイヤーボンディングにて電気的接続されていること、を特徴とする半導体基板。
- 金属板の第1の面に接続用ポストを有し、該金属板の第2の面に配線を有し、該接続用ポストと該配線と以外の領域がプリモールド用樹脂層で形成されたリードフレーム型基板であって、
該プリモールド樹脂の上面の高さが、接続用ポストの底面と同じ高さに成っていること、
を特徴とするリードフレーム型基板。
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008250860A JP5629969B2 (ja) | 2008-09-29 | 2008-09-29 | リードフレーム型基板の製造方法と半導体装置の製造方法 |
PCT/JP2009/004993 WO2010035509A1 (ja) | 2008-09-29 | 2009-09-29 | リードフレーム基板の製造方法と半導体装置 |
KR1020117006757A KR20110081955A (ko) | 2008-09-29 | 2009-09-29 | 리드 프레임 기판의 제조 방법과 반도체 장치 |
CN200980137966.7A CN102165581B (zh) | 2008-09-29 | 2009-09-29 | 引线框基板的制造方法 |
KR1020167003070A KR101613828B1 (ko) | 2008-09-29 | 2009-09-29 | 리드 프레임 기판의 제조 방법 |
US12/998,099 US8546940B2 (en) | 2008-09-29 | 2009-09-29 | Manufacturing method of lead frame substrate and semiconductor apparatus |
TW098132878A TWI521661B (zh) | 2008-09-29 | 2009-09-29 | 導線架基板之製造方法與半導體裝置 |
US14/038,114 US8703598B2 (en) | 2008-09-29 | 2013-09-26 | Manufacturing method of lead frame substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008250860A JP5629969B2 (ja) | 2008-09-29 | 2008-09-29 | リードフレーム型基板の製造方法と半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010086983A true JP2010086983A (ja) | 2010-04-15 |
JP5629969B2 JP5629969B2 (ja) | 2014-11-26 |
Family
ID=42059520
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008250860A Active JP5629969B2 (ja) | 2008-09-29 | 2008-09-29 | リードフレーム型基板の製造方法と半導体装置の製造方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US8546940B2 (ja) |
JP (1) | JP5629969B2 (ja) |
KR (2) | KR20110081955A (ja) |
CN (1) | CN102165581B (ja) |
TW (1) | TWI521661B (ja) |
WO (1) | WO2010035509A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013046168A (ja) * | 2011-08-23 | 2013-03-04 | Seiko Epson Corp | 振動デバイスの製造方法 |
JP2014150182A (ja) * | 2013-02-01 | 2014-08-21 | Denso Corp | 半導体装置の製造方法 |
KR101637189B1 (ko) * | 2015-06-12 | 2016-07-20 | 주식회사 에스에프에이반도체 | 반도체 패키지 제조방법 |
WO2023101044A1 (ko) * | 2021-11-30 | 2023-06-08 | 해성디에스 주식회사 | 프리 몰드 기판 및 프리 몰드 기판의 제조 방법 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8716873B2 (en) * | 2010-07-01 | 2014-05-06 | United Test And Assembly Center Ltd. | Semiconductor packages and methods of packaging semiconductor devices |
US9324584B2 (en) * | 2012-12-14 | 2016-04-26 | Stats Chippac Ltd. | Integrated circuit packaging system with transferable trace lead frame |
CN107113652B (zh) * | 2015-01-14 | 2020-08-18 | Lg 电子株式会社 | 确定是否分流业务到wlan的方法 |
US10666578B2 (en) * | 2016-09-06 | 2020-05-26 | Taiwan Semiconductor Manufacturing Company Limited | Network-on-chip system and a method of generating the same |
JP7406247B2 (ja) * | 2020-05-22 | 2023-12-27 | アピックヤマダ株式会社 | 樹脂モールド装置 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002289749A (ja) * | 2001-03-28 | 2002-10-04 | Hitachi Metals Ltd | 半導体素子搭載用配線板及びそれを用いた半導体素子搭載パッケージ |
JP2003309241A (ja) * | 2002-04-15 | 2003-10-31 | Dainippon Printing Co Ltd | リードフレーム部材とリードフレーム部材の製造方法、及び該リードフレーム部材を用いた半導体パッケージとその製造方法 |
JP2004063742A (ja) * | 2002-07-29 | 2004-02-26 | Hitachi Chem Co Ltd | 配線板、半導体パッケージ及びそれらの製造方法 |
JP2004119730A (ja) * | 2002-09-26 | 2004-04-15 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
JP2004281752A (ja) * | 2003-03-17 | 2004-10-07 | Sumitomo Bakelite Co Ltd | 片面回路基板の製造方法及び片面回路基板 |
JP2007324420A (ja) * | 2006-06-01 | 2007-12-13 | Tdk Corp | セラミック基板及び複合配線基板、並びにそれらの製造方法 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5976912A (en) * | 1994-03-18 | 1999-11-02 | Hitachi Chemical Company, Ltd. | Fabrication process of semiconductor package and semiconductor package |
US5656550A (en) * | 1994-08-24 | 1997-08-12 | Fujitsu Limited | Method of producing a semicondutor device having a lead portion with outer connecting terminal |
US5847458A (en) * | 1996-05-21 | 1998-12-08 | Shinko Electric Industries Co., Ltd. | Semiconductor package and device having heads coupled with insulating material |
DE69735588T2 (de) * | 1996-05-27 | 2007-01-11 | Dai Nippon Printing Co., Ltd. | Herstellung eines bauteils für eine halbleiterschaltung |
US6025640A (en) * | 1997-07-16 | 2000-02-15 | Dai Nippon Insatsu Kabushiki Kaisha | Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device |
US6782610B1 (en) * | 1999-05-21 | 2004-08-31 | North Corporation | Method for fabricating a wiring substrate by electroplating a wiring film on a metal base |
JP2001094026A (ja) * | 1999-09-22 | 2001-04-06 | Toshiba Corp | リードフレーム及びその製造方法 |
JP2002043467A (ja) * | 2000-07-31 | 2002-02-08 | Hitachi Chem Co Ltd | 半導体パッケージ用基板とその製造方法およびその基板を用いた半導体パッケージ並びに半導体パッケージの製造方法 |
US6762118B2 (en) * | 2000-10-10 | 2004-07-13 | Walsin Advanced Electronics Ltd. | Package having array of metal pegs linked by printed circuit lines |
JP2002222894A (ja) * | 2001-01-29 | 2002-08-09 | Hitachi Metals Ltd | 半導体用パッケージ |
TWI264099B (en) * | 2001-07-09 | 2006-10-11 | Sumitomo Metal Mining Co | Lead frame and manufacturing method therefor |
JP4052915B2 (ja) * | 2002-09-26 | 2008-02-27 | 三洋電機株式会社 | 回路装置の製造方法 |
JP2004119729A (ja) * | 2002-09-26 | 2004-04-15 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
JP4225036B2 (ja) * | 2002-11-20 | 2009-02-18 | 日本電気株式会社 | 半導体パッケージ及び積層型半導体パッケージ |
US6903449B2 (en) * | 2003-08-01 | 2005-06-07 | Micron Technology, Inc. | Semiconductor component having chip on board leadframe |
US7453157B2 (en) * | 2004-06-25 | 2008-11-18 | Tessera, Inc. | Microelectronic packages and methods therefor |
JP4305326B2 (ja) * | 2004-08-24 | 2009-07-29 | ソニー株式会社 | 半導体パッケージの製造方法 |
US7217991B1 (en) * | 2004-10-22 | 2007-05-15 | Amkor Technology, Inc. | Fan-in leadframe semiconductor package |
JP2006245618A (ja) | 2006-06-14 | 2006-09-14 | Fujitsu Ltd | 受動素子内蔵半導体装置 |
JP2009147117A (ja) * | 2007-12-14 | 2009-07-02 | Toppan Printing Co Ltd | リードフレーム型基板の製造方法及び半導体基板 |
GB0815870D0 (en) * | 2008-09-01 | 2008-10-08 | Cambridge Silicon Radio Ltd | Improved qfn package |
US8786062B2 (en) * | 2009-10-14 | 2014-07-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and process for fabricating same |
US8193037B1 (en) * | 2010-12-06 | 2012-06-05 | Stats Chippac Ltd. | Integrated circuit packaging system with pad connection and method of manufacture thereof |
-
2008
- 2008-09-29 JP JP2008250860A patent/JP5629969B2/ja active Active
-
2009
- 2009-09-29 KR KR1020117006757A patent/KR20110081955A/ko active Application Filing
- 2009-09-29 US US12/998,099 patent/US8546940B2/en not_active Expired - Fee Related
- 2009-09-29 KR KR1020167003070A patent/KR101613828B1/ko not_active IP Right Cessation
- 2009-09-29 CN CN200980137966.7A patent/CN102165581B/zh not_active Expired - Fee Related
- 2009-09-29 TW TW098132878A patent/TWI521661B/zh not_active IP Right Cessation
- 2009-09-29 WO PCT/JP2009/004993 patent/WO2010035509A1/ja active Application Filing
-
2013
- 2013-09-26 US US14/038,114 patent/US8703598B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002289749A (ja) * | 2001-03-28 | 2002-10-04 | Hitachi Metals Ltd | 半導体素子搭載用配線板及びそれを用いた半導体素子搭載パッケージ |
JP2003309241A (ja) * | 2002-04-15 | 2003-10-31 | Dainippon Printing Co Ltd | リードフレーム部材とリードフレーム部材の製造方法、及び該リードフレーム部材を用いた半導体パッケージとその製造方法 |
JP2004063742A (ja) * | 2002-07-29 | 2004-02-26 | Hitachi Chem Co Ltd | 配線板、半導体パッケージ及びそれらの製造方法 |
JP2004119730A (ja) * | 2002-09-26 | 2004-04-15 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
JP2004281752A (ja) * | 2003-03-17 | 2004-10-07 | Sumitomo Bakelite Co Ltd | 片面回路基板の製造方法及び片面回路基板 |
JP2007324420A (ja) * | 2006-06-01 | 2007-12-13 | Tdk Corp | セラミック基板及び複合配線基板、並びにそれらの製造方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013046168A (ja) * | 2011-08-23 | 2013-03-04 | Seiko Epson Corp | 振動デバイスの製造方法 |
JP2014150182A (ja) * | 2013-02-01 | 2014-08-21 | Denso Corp | 半導体装置の製造方法 |
KR101637189B1 (ko) * | 2015-06-12 | 2016-07-20 | 주식회사 에스에프에이반도체 | 반도체 패키지 제조방법 |
WO2023101044A1 (ko) * | 2021-11-30 | 2023-06-08 | 해성디에스 주식회사 | 프리 몰드 기판 및 프리 몰드 기판의 제조 방법 |
Also Published As
Publication number | Publication date |
---|---|
TWI521661B (zh) | 2016-02-11 |
JP5629969B2 (ja) | 2014-11-26 |
WO2010035509A1 (ja) | 2010-04-01 |
US20140021162A1 (en) | 2014-01-23 |
KR20160021304A (ko) | 2016-02-24 |
US20110169145A1 (en) | 2011-07-14 |
US8703598B2 (en) | 2014-04-22 |
US8546940B2 (en) | 2013-10-01 |
KR101613828B1 (ko) | 2016-04-19 |
CN102165581A (zh) | 2011-08-24 |
TW201019446A (en) | 2010-05-16 |
CN102165581B (zh) | 2015-12-16 |
KR20110081955A (ko) | 2011-07-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5629969B2 (ja) | リードフレーム型基板の製造方法と半導体装置の製造方法 | |
KR101615789B1 (ko) | 반도체 소자용 기판의 제조 방법 및 반도체 장치 | |
TWI404188B (zh) | 半導體元件用基板之製造方法及半導體裝置 | |
JP5672652B2 (ja) | 半導体素子用基板の製造方法および半導体装置 | |
JP2009267163A (ja) | 配線基板、半導体装置、ならびに半導体装置の製造方法 | |
JP2009147117A (ja) | リードフレーム型基板の製造方法及び半導体基板 | |
KR20120010044A (ko) | 리드프레임 제조방법과 그에 따른 리드프레임 및 반도체 패키지 제조방법과 그에 따른 반도체 패키지 | |
KR101674536B1 (ko) | 리드프레임을 이용한 회로 기판의 제조 방법 | |
JP5521301B2 (ja) | リードフレーム型基板とその製造方法および半導体装置 | |
KR101187913B1 (ko) | 반도체 패키지용 리이드 프레임과, 이를 제조하는 방법 | |
JP2017130522A (ja) | 樹脂付リードフレーム基板 | |
JP2016122713A (ja) | リードフレーム基板およびその製造方法 | |
JP6589577B2 (ja) | 樹脂付リードフレーム基板の製造方法 | |
KR101047874B1 (ko) | 리드프레임 및 반도체 패키지 및 그의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110825 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130813 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131008 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140624 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140820 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140909 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140922 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5629969 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |