JP2010050259A - 3次元積層半導体装置 - Google Patents
3次元積層半導体装置 Download PDFInfo
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
【解決手段】支持基板80の上に、基板を貫通するプラグ210a、210bが設けられた第1層の半導体チップ11を、表面側(回路領域110が設けられた側)を下向きにして電気的接続を行う。続いて、基板を貫通するプラグ210a、210bが設けられた第2層の半導体チップを、同様に積層し電気的接続を行う。支持基板80と第1層半導体チップ間、および半導体チップの各層間のスペースには、熱伝導率が金属並みに高い特性を有するカーボン・ナノチューブを含む樹脂膜を設ける。
【選択図】図1
Description
(第1の実施の形態)
(第2の実施の形態)
(第3の実施の形態)
(製造工程1)
(製造工程2)
3 導電層
4 補強構造体
23 貫通電極
32 低弾性金属材料
50 配線基板
53 貫通配線
54 ハンダボール
55 電極
56 金属バンプ
80 支持基板
100 半導体基板
110 回路素子等が設けられた領域
120、150 絶縁膜
150 貫通孔
200 配線パッド
210 貫通プラグ
250、251 バンプ金属
300 カーボン・ナノチューブを含む樹脂膜
310 空隙
350 絶縁性の樹脂膜
400 フォトレジスト
Claims (8)
- 電極が設けられた支持基板上に、回路と複数の貫通電極が設けられた半導体チップが、横並びに又は縦方向に少なくとも1個積層され、前記貫通電極を介して前記支持基板と少なくとも1個の前記半導体チップとを、金属バンプで相互に接続する3次元積層半導体装置において、
前記支持基板と前記半導体チップ間、および前記半導体チップ間のスペースの、少なくとも1層のスペースに、カーボン・ナノチューブを分散含有する樹脂材を挟み込むことを特徴とした3次元積層半導体装置。 - 前記支持基板と前記半導体チップの貫通電極とを接続する接続部が、前記カーボン・ナノチューブを分散含有する樹脂材と少なくとも接触しない距離を持って設けられることを特徴とした、請求項1記載の3次元積層半導体装置。
- 前記支持基板が、シリコン基板に貫通配線を設けたシリコン・インターポーザであることを特徴とした、請求項1又は請求項2に記載の3次元積層半導体装置。
- 前記支持基板が、回路が設けられた半導体チップであることを特徴とした、請求項1又は請求項2に記載の3次元積層半導体装置。
- 前記回路と複数の貫通電極が設けられた半導体チップに設けられた前記貫通電極が、信号伝達に加えて放熱も行うことを特徴とした、請求項1〜請求項4のいずれか1項に記載の3次元積層半導体装置。
- 請求項1、又は3、又は4のいずれか1項に記載の前記支持基板と、前記回路と複数の貫通電極が設けられた半導体チップとを接続する前記接続部の表面、および該支持基板の表面、および複数の該半導体チップの表面と裏面が、絶縁膜で覆われたことを特徴とした、請求項1、又は3、又は4のいずれか1項に記載の3次元積層半導体装置。
- 前記回路と複数の貫通電極が設けられた半導体チップが積層された最上層に、カーボン・ナノチューブを分散含有する樹脂材で放熱板を固着せしめることを特徴とした、請求項1〜請求項6のいずれか1項に記載の3次元積層半導体装置。
- 前記回路と複数の貫通電極が設けられた半導体チップの前記貫通電極は、絶縁膜により該半導体チップ間が電気的に絶縁されることを特徴とした請求項1〜請求項7のいずれか1項に記載の3次元積層半導体装置。
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JP2008212772A JP2010050259A (ja) | 2008-08-21 | 2008-08-21 | 3次元積層半導体装置 |
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Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102412212A (zh) * | 2010-09-21 | 2012-04-11 | 王维汉 | 电子/光电组件的散热装置 |
JP2012216836A (ja) * | 2011-03-31 | 2012-11-08 | Mitsubishi Chemicals Corp | 三次元集積回路積層体 |
JP2012238752A (ja) * | 2011-05-12 | 2012-12-06 | Internatl Business Mach Corp <Ibm> | シリコンボードにおけるシリコン貫通配線(tsv)の形成 |
WO2013014542A1 (en) * | 2011-07-22 | 2013-01-31 | International Business Machines Corporation | A system and method to process horizontally aligned graphite nanofibers in a thermal interface material used in 3d chip stacks |
US8367478B2 (en) | 2011-06-02 | 2013-02-05 | International Business Machines Corporation | Method and system for internal layer-layer thermal enhancement |
US8431048B2 (en) | 2010-07-23 | 2013-04-30 | International Business Machines Corporation | Method and system for alignment of graphite nanofibers for enhanced thermal interface material performance |
US20140210068A1 (en) * | 2013-01-30 | 2014-07-31 | International Business Machines Corporation | Horizontally aligned graphite nanofibers in etched silicon wafer troughs for enhanced thermal performance |
KR20150005199A (ko) * | 2013-07-05 | 2015-01-14 | 에스케이하이닉스 주식회사 | 반도체 칩 및 이를 갖는 적층형 반도체 패키지 |
US9082744B2 (en) | 2013-07-08 | 2015-07-14 | International Business Machines Corporation | Method for aligning carbon nanotubes containing magnetic nanoparticles in a thermosetting polymer using a magnetic field |
US9090004B2 (en) | 2013-02-06 | 2015-07-28 | International Business Machines Corporation | Composites comprised of aligned carbon fibers in chain-aligned polymer binder |
US9096784B2 (en) | 2010-07-23 | 2015-08-04 | International Business Machines Corporation | Method and system for allignment of graphite nanofibers for enhanced thermal interface material performance |
US9111899B2 (en) | 2012-09-13 | 2015-08-18 | Lenovo | Horizontally and vertically aligned graphite nanofibers thermal interface material for use in chip stacks |
CN109411373A (zh) * | 2018-09-18 | 2019-03-01 | 中国工程物理研究院电子工程研究所 | 一种采用载体支撑实现多层基板三维堆叠的方法 |
CN110648924A (zh) * | 2019-09-04 | 2020-01-03 | 广东芯华微电子技术有限公司 | 大板扇出型芯片封装结构及其制作方法 |
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JP2009246258A (ja) * | 2008-03-31 | 2009-10-22 | Nikon Corp | 半導体装置および製造方法 |
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2008
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JP2006222252A (ja) * | 2005-02-10 | 2006-08-24 | Elpida Memory Inc | 半導体記憶装置及びその負荷試験方法 |
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Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8431048B2 (en) | 2010-07-23 | 2013-04-30 | International Business Machines Corporation | Method and system for alignment of graphite nanofibers for enhanced thermal interface material performance |
US9096784B2 (en) | 2010-07-23 | 2015-08-04 | International Business Machines Corporation | Method and system for allignment of graphite nanofibers for enhanced thermal interface material performance |
CN102412212A (zh) * | 2010-09-21 | 2012-04-11 | 王维汉 | 电子/光电组件的散热装置 |
JP2012216836A (ja) * | 2011-03-31 | 2012-11-08 | Mitsubishi Chemicals Corp | 三次元集積回路積層体 |
JP2012238752A (ja) * | 2011-05-12 | 2012-12-06 | Internatl Business Mach Corp <Ibm> | シリコンボードにおけるシリコン貫通配線(tsv)の形成 |
US9385039B2 (en) | 2011-05-12 | 2016-07-05 | International Business Machines Corporation | Formation of through-silicon via (TSV) in silicon substrate |
US8367478B2 (en) | 2011-06-02 | 2013-02-05 | International Business Machines Corporation | Method and system for internal layer-layer thermal enhancement |
GB2506534B (en) * | 2011-07-22 | 2015-05-06 | Ibm | A system and method to process horizontally aligned graphite nanofibers in a thermal interface material used in 3d chip stacks |
GB2506534A (en) * | 2011-07-22 | 2014-04-02 | Ibm | A system and method to process horizontally aligned graphite nanofibers in a thermal interface material used in 3d chip stacks |
WO2013014542A1 (en) * | 2011-07-22 | 2013-01-31 | International Business Machines Corporation | A system and method to process horizontally aligned graphite nanofibers in a thermal interface material used in 3d chip stacks |
CN103748681A (zh) * | 2011-07-22 | 2014-04-23 | 国际商业机器公司 | 在3d芯片堆叠中所用热界面材料中处理水平排列石墨纳米纤维的系统和方法 |
US9257359B2 (en) | 2011-07-22 | 2016-02-09 | International Business Machines Corporation | System and method to process horizontally aligned graphite nanofibers in a thermal interface material used in 3D chip stacks |
US9111899B2 (en) | 2012-09-13 | 2015-08-18 | Lenovo | Horizontally and vertically aligned graphite nanofibers thermal interface material for use in chip stacks |
US20140210068A1 (en) * | 2013-01-30 | 2014-07-31 | International Business Machines Corporation | Horizontally aligned graphite nanofibers in etched silicon wafer troughs for enhanced thermal performance |
US9245813B2 (en) | 2013-01-30 | 2016-01-26 | International Business Machines Corporation | Horizontally aligned graphite nanofibers in etched silicon wafer troughs for enhanced thermal performance |
US9090004B2 (en) | 2013-02-06 | 2015-07-28 | International Business Machines Corporation | Composites comprised of aligned carbon fibers in chain-aligned polymer binder |
KR20150005199A (ko) * | 2013-07-05 | 2015-01-14 | 에스케이하이닉스 주식회사 | 반도체 칩 및 이를 갖는 적층형 반도체 패키지 |
KR102057210B1 (ko) * | 2013-07-05 | 2020-01-22 | 에스케이하이닉스 주식회사 | 반도체 칩 및 이를 갖는 적층형 반도체 패키지 |
US9082744B2 (en) | 2013-07-08 | 2015-07-14 | International Business Machines Corporation | Method for aligning carbon nanotubes containing magnetic nanoparticles in a thermosetting polymer using a magnetic field |
US9406651B2 (en) | 2013-07-08 | 2016-08-02 | Globalfoundries Inc. | Chip stack with oleic acid-aligned nanotubes in thermal interface material |
CN109411373A (zh) * | 2018-09-18 | 2019-03-01 | 中国工程物理研究院电子工程研究所 | 一种采用载体支撑实现多层基板三维堆叠的方法 |
CN110648924A (zh) * | 2019-09-04 | 2020-01-03 | 广东芯华微电子技术有限公司 | 大板扇出型芯片封装结构及其制作方法 |
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