JP2010021516A - 電子素子内蔵型印刷回路基板の製造方法 - Google Patents
電子素子内蔵型印刷回路基板の製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 229920005989 resin Polymers 0.000 claims abstract description 54
- 239000011347 resin Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 41
- 239000012212 insulator Substances 0.000 claims abstract description 23
- 238000010030 laminating Methods 0.000 claims abstract description 8
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 239000003365 glass fiber Substances 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 7
- 239000011295 pitch Substances 0.000 abstract 2
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 13
- 239000010410 layer Substances 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- B32B2038/0016—Abrading
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Abstract
【解決手段】ボンディングシート20の上面に、上面に電極11bが形成された電子素子を搭載するステップと、電子素子に対応するキャビティが形成された絶縁体30をボンディングシート20の上面に搭載するステップと、電子素子の上面を覆うように、絶縁体30の上面に第1絶縁樹脂を積層するステップと、電極11bが露出するように第1絶縁樹脂を研磨するステップと、研磨された第1絶縁樹脂41に、露出された電極11bと電気的に接続される第1回路パターン51を形成するステップと、を含むことを特徴とする。
【選択図】図10
Description
11a,11b,11c 電極
20 ボンディングシート
30 絶縁体
32 キャビティ
41 第1絶縁樹脂
42 第2絶縁樹脂
51 第1回路パターン
52 第2回路パターン
53 ビアホール
Claims (6)
- ボンディングシートの上面に、上面に電極が形成された電子素子を搭載するステップと、
前記電子素子に対応するキャビティが形成された絶縁体を前記ボンディングシートの上面に搭載するステップと、
前記電子素子の上面を覆うように前記絶縁体の上面に第1絶縁樹脂を積層するステップと、
前記電極が露出するように前記第1絶縁樹脂を研磨するステップと、
前記研磨された第1絶縁樹脂に、前記露出している電極と電気的に接続される第1回路パターンを形成するステップと、
を含む電子素子内蔵型印刷回路基板の製造方法。 - 前記第1絶縁樹脂から前記ボンディングシートを貫通するビアを形成するステップと、
前記ボンディングシートの下面に第2回路パターンを形成するステップと、
をさらに含む請求項1に記載の電子素子内蔵型印刷回路基板の製造方法。 - 前記ボンディングシートの下面に第2絶縁樹脂を積層するステップと、
前記第1絶縁樹脂から前記第2絶縁樹脂を貫通するビアを形成するステップと、
前記絶縁樹脂の下面に第2回路パターンを形成するステップと、 をさらに含む請求項1に記載の電子素子内蔵型印刷回路基板の製造方法。 - 前記第1絶縁樹脂が、前記第2絶縁樹脂より厚いことを特徴とする請求項3に記載の電子素子内蔵型印刷回路基板の製造方法。
- 前記ボンディングシートは、ガラス繊維が含浸されたエポキシ樹脂からなることを特徴とする請求項1から請求項4の何れかに記載の電子素子内蔵型印刷回路基板の製造方法。
- 前記キャビティが形成された絶縁体は、硬化された(C−stage)状態であることを特徴とする請求項1から請求項5の何れかに記載の電子素子内蔵型印刷回路基板の製造方法。
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KR1020080066918A KR100982795B1 (ko) | 2008-07-10 | 2008-07-10 | 전자소자 내장형 인쇄회로기판 제조방법 |
KR10-2008-0066918 | 2008-07-10 |
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JP2010021516A true JP2010021516A (ja) | 2010-01-28 |
JP5219276B2 JP5219276B2 (ja) | 2013-06-26 |
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JP2009011407A Expired - Fee Related JP5219276B2 (ja) | 2008-07-10 | 2009-01-21 | 電子素子内蔵型印刷回路基板の製造方法 |
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US (1) | US8206530B2 (ja) |
JP (1) | JP5219276B2 (ja) |
KR (1) | KR100982795B1 (ja) |
TW (1) | TWI454192B (ja) |
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JP2011146547A (ja) * | 2010-01-15 | 2011-07-28 | Murata Mfg Co Ltd | 回路モジュール |
KR101085733B1 (ko) * | 2010-05-28 | 2011-11-21 | 삼성전기주식회사 | 전자소자 내장 인쇄회로기판 및 그 제조방법 |
KR101053633B1 (ko) | 2010-06-23 | 2011-08-03 | 엘지전자 주식회사 | 모듈식 조명장치 |
KR101216084B1 (ko) | 2010-06-23 | 2012-12-26 | 엘지전자 주식회사 | 조명장치 및 모듈식 조명장치 |
KR101057064B1 (ko) | 2010-06-30 | 2011-08-16 | 엘지전자 주식회사 | 엘이디 조명장치 및 그 제조방법 |
KR101053634B1 (ko) | 2010-07-02 | 2011-08-03 | 엘지전자 주식회사 | 엘이디 조명장치 및 그 제조방법 |
KR20120026855A (ko) | 2010-09-10 | 2012-03-20 | 삼성전기주식회사 | 임베디드 볼 그리드 어레이 기판 및 그 제조 방법 |
JP2013106032A (ja) * | 2011-11-14 | 2013-05-30 | Sda Co Ltd | クリアランス・フィリング・pcb及びその製造方法 |
US20130256007A1 (en) * | 2012-03-28 | 2013-10-03 | Ibiden Co., Ltd. | Wiring board with built-in electronic component and method for manufacturing the same |
CN103732012B (zh) * | 2012-10-15 | 2016-11-16 | 景硕科技股份有限公司 | 线路载板的增层方法 |
US9240392B2 (en) * | 2014-04-09 | 2016-01-19 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co., Ltd. | Method for fabricating embedded chips |
KR102139755B1 (ko) * | 2015-01-22 | 2020-07-31 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
CN104837297B (zh) * | 2015-05-27 | 2018-10-19 | 维沃移动通信有限公司 | 一种电路板及电子设备 |
CN106783795A (zh) * | 2015-11-20 | 2017-05-31 | 恒劲科技股份有限公司 | 封装基板 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07212002A (ja) * | 1994-01-12 | 1995-08-11 | At & T Corp | グリッドアレイ・プラスチックパッケージ、およびその製造方法、およびその製造に使用されるプラスチック積層体、およびその製造方法 |
JPH10270858A (ja) * | 1997-03-28 | 1998-10-09 | Hitachi Chem Co Ltd | 多層配線板及びその製造法 |
JP2002185145A (ja) * | 2000-12-15 | 2002-06-28 | Ibiden Co Ltd | 多層プリント配線板およびその製造方法 |
JP2004228397A (ja) * | 2003-01-24 | 2004-08-12 | Cmk Corp | 積層チップコンデンサを内蔵した多層プリント配線板の製造方法 |
JP2006237337A (ja) * | 2005-02-25 | 2006-09-07 | Cmk Corp | 半導体装置及びその製造方法 |
JP2006269594A (ja) * | 2005-03-23 | 2006-10-05 | Cmk Corp | 半導体装置及びその製造方法 |
JP2007288109A (ja) * | 2006-04-20 | 2007-11-01 | Cmk Corp | 半導体装置及びその製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1196392C (zh) * | 2000-07-31 | 2005-04-06 | 日本特殊陶业株式会社 | 布线基板及其制造方法 |
JP2002179772A (ja) * | 2000-12-08 | 2002-06-26 | Mitsui Mining & Smelting Co Ltd | プリント配線板の層間絶縁層構成用の樹脂化合物、その樹脂化合物を用いた絶縁層形成用樹脂シート及び樹脂付銅箔、並びにそれらを用いた銅張積層板 |
US6512182B2 (en) * | 2001-03-12 | 2003-01-28 | Ngk Spark Plug Co., Ltd. | Wiring circuit board and method for producing same |
JP4226981B2 (ja) * | 2003-09-24 | 2009-02-18 | 三井金属鉱業株式会社 | プリント配線板の製造方法及びその製造方法で得られたプリント配線板 |
KR100747022B1 (ko) | 2006-01-20 | 2007-08-07 | 삼성전기주식회사 | 임베디드 인쇄회로기판 및 그 제작방법 |
KR100650707B1 (ko) | 2006-01-25 | 2006-11-28 | 삼성전기주식회사 | 임베디드 인쇄회로기판 및 그 제작 방법 |
KR100758229B1 (ko) | 2006-04-11 | 2007-09-12 | 삼성전기주식회사 | 전자소자 내장 인쇄회로기판 및 그 제조방법 |
US7935893B2 (en) * | 2008-02-14 | 2011-05-03 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board with built-in electronic component |
US8261435B2 (en) * | 2008-12-29 | 2012-09-11 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
-
2008
- 2008-07-10 KR KR1020080066918A patent/KR100982795B1/ko not_active IP Right Cessation
-
2009
- 2009-01-07 TW TW098100402A patent/TWI454192B/zh not_active IP Right Cessation
- 2009-01-09 US US12/351,261 patent/US8206530B2/en not_active Expired - Fee Related
- 2009-01-21 JP JP2009011407A patent/JP5219276B2/ja not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07212002A (ja) * | 1994-01-12 | 1995-08-11 | At & T Corp | グリッドアレイ・プラスチックパッケージ、およびその製造方法、およびその製造に使用されるプラスチック積層体、およびその製造方法 |
JPH10270858A (ja) * | 1997-03-28 | 1998-10-09 | Hitachi Chem Co Ltd | 多層配線板及びその製造法 |
JP2002185145A (ja) * | 2000-12-15 | 2002-06-28 | Ibiden Co Ltd | 多層プリント配線板およびその製造方法 |
JP2004228397A (ja) * | 2003-01-24 | 2004-08-12 | Cmk Corp | 積層チップコンデンサを内蔵した多層プリント配線板の製造方法 |
JP2006237337A (ja) * | 2005-02-25 | 2006-09-07 | Cmk Corp | 半導体装置及びその製造方法 |
JP2006269594A (ja) * | 2005-03-23 | 2006-10-05 | Cmk Corp | 半導体装置及びその製造方法 |
JP2007288109A (ja) * | 2006-04-20 | 2007-11-01 | Cmk Corp | 半導体装置及びその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USD737724S1 (en) * | 2014-05-13 | 2015-09-01 | Honda Motor Co., Ltd. | All-terrain vehicle |
Also Published As
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TW201004504A (en) | 2010-01-16 |
KR20100006685A (ko) | 2010-01-21 |
KR100982795B1 (ko) | 2010-09-16 |
US8206530B2 (en) | 2012-06-26 |
TWI454192B (zh) | 2014-09-21 |
US20100006203A1 (en) | 2010-01-14 |
JP5219276B2 (ja) | 2013-06-26 |
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