JP2009540302A5 - - Google Patents

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Publication number
JP2009540302A5
JP2009540302A5 JP2009514561A JP2009514561A JP2009540302A5 JP 2009540302 A5 JP2009540302 A5 JP 2009540302A5 JP 2009514561 A JP2009514561 A JP 2009514561A JP 2009514561 A JP2009514561 A JP 2009514561A JP 2009540302 A5 JP2009540302 A5 JP 2009540302A5
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JP
Japan
Prior art keywords
input
core
logic block
scan
user
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JP2009514561A
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English (en)
Japanese (ja)
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JP2009540302A (ja
JP5131997B2 (ja
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Priority claimed from PCT/US2007/070821 external-priority patent/WO2007146849A1/en
Publication of JP2009540302A publication Critical patent/JP2009540302A/ja
Publication of JP2009540302A5 publication Critical patent/JP2009540302A5/ja
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Publication of JP5131997B2 publication Critical patent/JP5131997B2/ja
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JP2009514561A 2006-06-09 2007-06-09 透過的なテスト法及びスキャンフリップフロップ Active JP5131997B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US80428306P 2006-06-09 2006-06-09
US60/804,283 2006-06-09
US80508706P 2006-06-18 2006-06-18
US60/805,087 2006-06-18
PCT/US2007/070821 WO2007146849A1 (en) 2006-06-09 2007-06-09 Transparent test method and scan flip-flop

Publications (3)

Publication Number Publication Date
JP2009540302A JP2009540302A (ja) 2009-11-19
JP2009540302A5 true JP2009540302A5 (https=) 2010-07-22
JP5131997B2 JP5131997B2 (ja) 2013-01-30

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JP2009514561A Active JP5131997B2 (ja) 2006-06-09 2007-06-09 透過的なテスト法及びスキャンフリップフロップ

Country Status (5)

Country Link
US (1) US8122413B2 (https=)
EP (1) EP2030114B1 (https=)
JP (1) JP5131997B2 (https=)
KR (1) KR101006822B1 (https=)
WO (1) WO2007146849A1 (https=)

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JP5629309B2 (ja) * 2010-03-15 2014-11-19 株式会社日立製作所 半導体装置およびそのテスト方法
KR101709071B1 (ko) 2010-05-19 2017-02-22 삼성전자주식회사 컴프레션 모드 스캔 테스트를 위한 집적 회로
US8788896B2 (en) * 2012-01-11 2014-07-22 Lsi Corporation Scan chain lockup latch with data input control responsive to scan enable signal
US9086457B2 (en) * 2013-03-26 2015-07-21 International Business Machines Corporation Scan chain latch design that improves testability of integrated circuits
TWI508450B (zh) * 2013-04-10 2015-11-11 Mstar Semiconductor Inc 半動態正反器
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CN104809072A (zh) * 2013-06-28 2015-07-29 哈尔滨工业大学 基于Perl的EDIF网表级电路的自动可测性设计系统的自动可测性设计方法
US9793881B2 (en) * 2013-08-05 2017-10-17 Samsung Electronics Co., Ltd. Flip-flop with zero-delay bypass mux
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KR101697213B1 (ko) * 2014-09-02 2017-01-17 성균관대학교산학협력단 디지털 회로의 방사선 내성평가 시스템 및 방사선 내성평가 방법
US10317464B2 (en) * 2017-05-08 2019-06-11 Xilinx, Inc. Dynamic scan chain reconfiguration in an integrated circuit
US10936774B1 (en) * 2018-02-15 2021-03-02 Real Intent, Inc. Methods for identifying integrated circuit failures caused by reset-domain interactions
CN109884516B (zh) * 2019-01-29 2021-01-12 中国科学院微电子研究所 异步复位触发器验证电路以及集成电路验证装置
CN110262616B (zh) * 2019-05-22 2021-01-15 西安理工大学 一种超细粒度控制门级单元电源供应的方法
CN110601811B (zh) * 2019-09-12 2022-10-21 北京大学软件与微电子学院 一种在dft中使用的安全性的测试模式译码电路
CN111931445B (zh) * 2020-10-09 2020-12-29 芯华章科技股份有限公司 用于调试逻辑系统设计的方法、仿真器及存储介质
US11901902B2 (en) 2021-05-25 2024-02-13 Samsung Electronics Co., Ltd. Integrated circuit including flip-flop and computing system for designing the integrated circuit
US11782092B1 (en) 2022-05-18 2023-10-10 Stmicroelectronics International N.V. Scan compression through pin data encoding
US12480993B2 (en) 2024-03-18 2025-11-25 Stmicroelectronics International N.V. Low pin count scan with no dedicated scan enable pin

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