JP5131997B2 - 透過的なテスト法及びスキャンフリップフロップ - Google Patents

透過的なテスト法及びスキャンフリップフロップ Download PDF

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JP5131997B2
JP5131997B2 JP2009514561A JP2009514561A JP5131997B2 JP 5131997 B2 JP5131997 B2 JP 5131997B2 JP 2009514561 A JP2009514561 A JP 2009514561A JP 2009514561 A JP2009514561 A JP 2009514561A JP 5131997 B2 JP5131997 B2 JP 5131997B2
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input
output
scan
data input
dft
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JP2009540302A (ja
JP2009540302A5 (https=
Inventor
パット ホム
スティーヴン エプレット
ラビー セングプタ
エリック ウェスト
ライル スミス
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オトルソテック リミテッド ライアビリティ カンパニー
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C2029/3202—Scan chain

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2009514561A 2006-06-09 2007-06-09 透過的なテスト法及びスキャンフリップフロップ Active JP5131997B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US80428306P 2006-06-09 2006-06-09
US60/804,283 2006-06-09
US80508706P 2006-06-18 2006-06-18
US60/805,087 2006-06-18
PCT/US2007/070821 WO2007146849A1 (en) 2006-06-09 2007-06-09 Transparent test method and scan flip-flop

Publications (3)

Publication Number Publication Date
JP2009540302A JP2009540302A (ja) 2009-11-19
JP2009540302A5 JP2009540302A5 (https=) 2010-07-22
JP5131997B2 true JP5131997B2 (ja) 2013-01-30

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JP2009514561A Active JP5131997B2 (ja) 2006-06-09 2007-06-09 透過的なテスト法及びスキャンフリップフロップ

Country Status (5)

Country Link
US (1) US8122413B2 (https=)
EP (1) EP2030114B1 (https=)
JP (1) JP5131997B2 (https=)
KR (1) KR101006822B1 (https=)
WO (1) WO2007146849A1 (https=)

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JP5629309B2 (ja) * 2010-03-15 2014-11-19 株式会社日立製作所 半導体装置およびそのテスト方法
KR101709071B1 (ko) 2010-05-19 2017-02-22 삼성전자주식회사 컴프레션 모드 스캔 테스트를 위한 집적 회로
US8788896B2 (en) * 2012-01-11 2014-07-22 Lsi Corporation Scan chain lockup latch with data input control responsive to scan enable signal
US9086457B2 (en) * 2013-03-26 2015-07-21 International Business Machines Corporation Scan chain latch design that improves testability of integrated circuits
TWI508450B (zh) * 2013-04-10 2015-11-11 Mstar Semiconductor Inc 半動態正反器
CN104124946B (zh) * 2013-04-24 2016-10-05 晨星半导体股份有限公司 半动态触发器
CN104809072A (zh) * 2013-06-28 2015-07-29 哈尔滨工业大学 基于Perl的EDIF网表级电路的自动可测性设计系统的自动可测性设计方法
US9793881B2 (en) * 2013-08-05 2017-10-17 Samsung Electronics Co., Ltd. Flip-flop with zero-delay bypass mux
WO2015035144A1 (en) * 2013-09-06 2015-03-12 Blue Pearl Software, Inc. User grey cell
CN103530479B (zh) * 2013-10-31 2016-09-21 哈尔滨工业大学 基于Perl的EDIF网表级电路的部分可测性设计系统及部分可测性设计方法
CN103699422A (zh) * 2013-12-25 2014-04-02 哈尔滨工业大学 使用Perl语言对电路verilog网表描述进行可测性设计的系统及方法
KR101697213B1 (ko) * 2014-09-02 2017-01-17 성균관대학교산학협력단 디지털 회로의 방사선 내성평가 시스템 및 방사선 내성평가 방법
US10317464B2 (en) * 2017-05-08 2019-06-11 Xilinx, Inc. Dynamic scan chain reconfiguration in an integrated circuit
US10936774B1 (en) * 2018-02-15 2021-03-02 Real Intent, Inc. Methods for identifying integrated circuit failures caused by reset-domain interactions
CN109884516B (zh) * 2019-01-29 2021-01-12 中国科学院微电子研究所 异步复位触发器验证电路以及集成电路验证装置
CN110262616B (zh) * 2019-05-22 2021-01-15 西安理工大学 一种超细粒度控制门级单元电源供应的方法
CN110601811B (zh) * 2019-09-12 2022-10-21 北京大学软件与微电子学院 一种在dft中使用的安全性的测试模式译码电路
CN111931445B (zh) * 2020-10-09 2020-12-29 芯华章科技股份有限公司 用于调试逻辑系统设计的方法、仿真器及存储介质
US11901902B2 (en) 2021-05-25 2024-02-13 Samsung Electronics Co., Ltd. Integrated circuit including flip-flop and computing system for designing the integrated circuit
US11782092B1 (en) 2022-05-18 2023-10-10 Stmicroelectronics International N.V. Scan compression through pin data encoding
US12480993B2 (en) 2024-03-18 2025-11-25 Stmicroelectronics International N.V. Low pin count scan with no dedicated scan enable pin

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Also Published As

Publication number Publication date
JP2009540302A (ja) 2009-11-19
EP2030114B1 (en) 2013-01-23
KR20090051157A (ko) 2009-05-21
EP2030114A1 (en) 2009-03-04
US20100169856A1 (en) 2010-07-01
WO2007146849A1 (en) 2007-12-21
US8122413B2 (en) 2012-02-21
EP2030114A4 (en) 2011-05-18
KR101006822B1 (ko) 2011-01-10

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