KR101006822B1 - 투명한 테스트 방법 및 스캔 플립 플롭 - Google Patents

투명한 테스트 방법 및 스캔 플립 플롭 Download PDF

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KR101006822B1
KR101006822B1 KR1020097000531A KR20097000531A KR101006822B1 KR 101006822 B1 KR101006822 B1 KR 101006822B1 KR 1020097000531 A KR1020097000531 A KR 1020097000531A KR 20097000531 A KR20097000531 A KR 20097000531A KR 101006822 B1 KR101006822 B1 KR 101006822B1
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South Korea
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input
scan
dft
user
core
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Korean (ko)
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KR20090051157A (ko
Inventor
팻 홈
스티븐 에플렛
라비 센굽타
에릭 웨스트
라일 스미스
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오트르소테크, 엘엘씨
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C2029/3202—Scan chain

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1020097000531A 2006-06-09 2007-06-09 투명한 테스트 방법 및 스캔 플립 플롭 Active KR101006822B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US80428306P 2006-06-09 2006-06-09
US60/804,283 2006-06-09
US80508706P 2006-06-18 2006-06-18
US60/805,087 2006-06-18

Publications (2)

Publication Number Publication Date
KR20090051157A KR20090051157A (ko) 2009-05-21
KR101006822B1 true KR101006822B1 (ko) 2011-01-10

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KR1020097000531A Active KR101006822B1 (ko) 2006-06-09 2007-06-09 투명한 테스트 방법 및 스캔 플립 플롭

Country Status (5)

Country Link
US (1) US8122413B2 (https=)
EP (1) EP2030114B1 (https=)
JP (1) JP5131997B2 (https=)
KR (1) KR101006822B1 (https=)
WO (1) WO2007146849A1 (https=)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8332793B2 (en) 2006-05-18 2012-12-11 Otrsotech, Llc Methods and systems for placement and routing
US8667437B2 (en) * 2008-03-17 2014-03-04 Xilinx, Inc. Creating a standard cell circuit design from a programmable logic device circuit design
KR20100078431A (ko) * 2008-12-30 2010-07-08 주식회사 동부하이텍 표준 셀 라이브러리의 성능 개선을 위한 측정 장치
JP5629309B2 (ja) * 2010-03-15 2014-11-19 株式会社日立製作所 半導体装置およびそのテスト方法
KR101709071B1 (ko) 2010-05-19 2017-02-22 삼성전자주식회사 컴프레션 모드 스캔 테스트를 위한 집적 회로
US8788896B2 (en) * 2012-01-11 2014-07-22 Lsi Corporation Scan chain lockup latch with data input control responsive to scan enable signal
US9086457B2 (en) * 2013-03-26 2015-07-21 International Business Machines Corporation Scan chain latch design that improves testability of integrated circuits
TWI508450B (zh) * 2013-04-10 2015-11-11 Mstar Semiconductor Inc 半動態正反器
CN104124946B (zh) * 2013-04-24 2016-10-05 晨星半导体股份有限公司 半动态触发器
CN104809072A (zh) * 2013-06-28 2015-07-29 哈尔滨工业大学 基于Perl的EDIF网表级电路的自动可测性设计系统的自动可测性设计方法
US9793881B2 (en) * 2013-08-05 2017-10-17 Samsung Electronics Co., Ltd. Flip-flop with zero-delay bypass mux
WO2015035144A1 (en) * 2013-09-06 2015-03-12 Blue Pearl Software, Inc. User grey cell
CN103530479B (zh) * 2013-10-31 2016-09-21 哈尔滨工业大学 基于Perl的EDIF网表级电路的部分可测性设计系统及部分可测性设计方法
CN103699422A (zh) * 2013-12-25 2014-04-02 哈尔滨工业大学 使用Perl语言对电路verilog网表描述进行可测性设计的系统及方法
KR101697213B1 (ko) * 2014-09-02 2017-01-17 성균관대학교산학협력단 디지털 회로의 방사선 내성평가 시스템 및 방사선 내성평가 방법
US10317464B2 (en) * 2017-05-08 2019-06-11 Xilinx, Inc. Dynamic scan chain reconfiguration in an integrated circuit
US10936774B1 (en) * 2018-02-15 2021-03-02 Real Intent, Inc. Methods for identifying integrated circuit failures caused by reset-domain interactions
CN109884516B (zh) * 2019-01-29 2021-01-12 中国科学院微电子研究所 异步复位触发器验证电路以及集成电路验证装置
CN110262616B (zh) * 2019-05-22 2021-01-15 西安理工大学 一种超细粒度控制门级单元电源供应的方法
CN110601811B (zh) * 2019-09-12 2022-10-21 北京大学软件与微电子学院 一种在dft中使用的安全性的测试模式译码电路
CN111931445B (zh) * 2020-10-09 2020-12-29 芯华章科技股份有限公司 用于调试逻辑系统设计的方法、仿真器及存储介质
US11901902B2 (en) 2021-05-25 2024-02-13 Samsung Electronics Co., Ltd. Integrated circuit including flip-flop and computing system for designing the integrated circuit
US11782092B1 (en) 2022-05-18 2023-10-10 Stmicroelectronics International N.V. Scan compression through pin data encoding
US12480993B2 (en) 2024-03-18 2025-11-25 Stmicroelectronics International N.V. Low pin count scan with no dedicated scan enable pin

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040194046A1 (en) 2003-03-27 2004-09-30 Tempus Fugit Inc. Trace based method for design navigation
US20040230933A1 (en) 2003-05-15 2004-11-18 Weaver Edward G. Tool flow process for physical design of integrated circuits
US20060085709A1 (en) 2004-10-02 2006-04-20 Kim Chung-Hee Flip flop circuit & same with scan function
KR20060066634A (ko) * 2004-12-13 2006-06-16 양세양 검증 성능과 검증 효율성을 높이는 동적검증 기법 방식의검증 장치 및 이를 이용한 검증 방법론

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63300528A (ja) 1987-05-29 1988-12-07 Nec Corp ゲ−トアレイ集積回路
JP2945103B2 (ja) 1990-05-15 1999-09-06 株式会社リコー テスト用スキャン回路装置
US5166604A (en) * 1990-11-13 1992-11-24 Altera Corporation Methods and apparatus for facilitating scan testing of asynchronous logic circuitry
JPH05341016A (ja) 1992-06-11 1993-12-24 Seiko Epson Corp 半導体集積回路装置およびテスト方法
US6096567A (en) 1997-12-01 2000-08-01 Electroglas, Inc. Method and apparatus for direct probe sensing
JP3556502B2 (ja) 1999-01-20 2004-08-18 松下電器産業株式会社 Ｄ型フリップフロップ
US6393592B1 (en) * 1999-05-21 2002-05-21 Adaptec, Inc. Scan flop circuitry and methods for making the same
US6701491B1 (en) * 1999-06-26 2004-03-02 Sei-Yang Yang Input/output probing apparatus and input/output probing method using the same, and mixed emulation/simulation method based on it
JP4428489B2 (ja) * 1999-08-23 2010-03-10 パナソニック株式会社 集積回路装置及びそのテスト方法
JP3699019B2 (ja) * 2001-08-01 2005-09-28 Ｎｅｃマイクロシステム株式会社 スキャン用フリップフロップおよびスキャンテスト回路
US7127695B2 (en) * 2002-07-18 2006-10-24 Incentia Design Systems Corp. Timing based scan chain implementation in an IC design
FR2842913B1 (fr) * 2002-07-23 2004-11-19 Schlumberger Services Petrol Dispositif compact de mesure de vitesse et de sens de rotation d'un objet
US6938225B2 (en) * 2002-09-04 2005-08-30 Intel Corporation Scan design for double-edge-triggered flip-flops
US7313739B2 (en) * 2002-12-31 2007-12-25 Analog Devices, Inc. Method and apparatus for testing embedded cores
US7134061B2 (en) * 2003-09-08 2006-11-07 Texas Instruments Incorporated At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform
KR20050051856A (ko) * 2003-11-28 2005-06-02 삼성전자주식회사 디버깅용 주사 체인을 가지는 반도체 장치 및 주사 체인을이용한 디버깅 방법
US7030651B2 (en) * 2003-12-04 2006-04-18 Viciciv Technology Programmable structured arrays

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040194046A1 (en) 2003-03-27 2004-09-30 Tempus Fugit Inc. Trace based method for design navigation
US20040230933A1 (en) 2003-05-15 2004-11-18 Weaver Edward G. Tool flow process for physical design of integrated circuits
US20060085709A1 (en) 2004-10-02 2006-04-20 Kim Chung-Hee Flip flop circuit & same with scan function
KR20060066634A (ko) * 2004-12-13 2006-06-16 양세양 검증 성능과 검증 효율성을 높이는 동적검증 기법 방식의검증 장치 및 이를 이용한 검증 방법론

Also Published As

Publication number Publication date
JP2009540302A (ja) 2009-11-19
EP2030114B1 (en) 2013-01-23
KR20090051157A (ko) 2009-05-21
EP2030114A1 (en) 2009-03-04
US20100169856A1 (en) 2010-07-01
WO2007146849A1 (en) 2007-12-21
US8122413B2 (en) 2012-02-21
EP2030114A4 (en) 2011-05-18
JP5131997B2 (ja) 2013-01-30

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