JP2009532912A - 一体型スルーホール熱放散ピンを有するモールドされた半導体パッケージ - Google Patents

一体型スルーホール熱放散ピンを有するモールドされた半導体パッケージ Download PDF

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Publication number
JP2009532912A
JP2009532912A JP2009504367A JP2009504367A JP2009532912A JP 2009532912 A JP2009532912 A JP 2009532912A JP 2009504367 A JP2009504367 A JP 2009504367A JP 2009504367 A JP2009504367 A JP 2009504367A JP 2009532912 A JP2009532912 A JP 2009532912A
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Prior art keywords
heat dissipation
pad
pin
exposed
die
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JP2009504367A
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Japanese (ja)
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JP2009532912A5 (enExample
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バウアー、ロベルト
コルベック、アントン
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NXP USA Inc
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NXP USA Inc
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Publication of JP2009532912A publication Critical patent/JP2009532912A/ja
Publication of JP2009532912A5 publication Critical patent/JP2009532912A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2009504367A 2006-04-06 2007-03-12 一体型スルーホール熱放散ピンを有するモールドされた半導体パッケージ Pending JP2009532912A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/398,944 US7772036B2 (en) 2006-04-06 2006-04-06 Lead frame based, over-molded semiconductor package with integrated through hole technology (THT) heat spreader pin(s) and associated method of manufacturing
PCT/US2007/063777 WO2007117819A2 (en) 2006-04-06 2007-03-12 Molded semiconductor package with integrated through hole heat spreader pin(s)

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013164657A Division JP2014013908A (ja) 2006-04-06 2013-08-08 一体型スルーホール熱放散ピンを有するモールドされた半導体パッケージおよびその製造方法

Publications (2)

Publication Number Publication Date
JP2009532912A true JP2009532912A (ja) 2009-09-10
JP2009532912A5 JP2009532912A5 (enExample) 2010-03-11

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JP2009504367A Pending JP2009532912A (ja) 2006-04-06 2007-03-12 一体型スルーホール熱放散ピンを有するモールドされた半導体パッケージ
JP2013164657A Pending JP2014013908A (ja) 2006-04-06 2013-08-08 一体型スルーホール熱放散ピンを有するモールドされた半導体パッケージおよびその製造方法

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JP2013164657A Pending JP2014013908A (ja) 2006-04-06 2013-08-08 一体型スルーホール熱放散ピンを有するモールドされた半導体パッケージおよびその製造方法

Country Status (6)

Country Link
US (2) US7772036B2 (enExample)
EP (1) EP2005470B1 (enExample)
JP (2) JP2009532912A (enExample)
KR (1) KR101388328B1 (enExample)
CN (1) CN101416305B (enExample)
WO (1) WO2007117819A2 (enExample)

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JP2011040507A (ja) * 2009-08-07 2011-02-24 Sumitomo Wiring Syst Ltd 回路装置
WO2018092185A1 (ja) * 2016-11-15 2018-05-24 三菱電機株式会社 半導体モジュール及び半導体装置
WO2020262957A1 (ko) * 2019-06-24 2020-12-30 안상정 반도체 발광소자용 지지 기판을 제조하는 방법

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US8966747B2 (en) 2011-05-11 2015-03-03 Vlt, Inc. Method of forming an electrical contact
CN104900623B (zh) 2014-03-06 2018-11-30 恩智浦美国有限公司 露出管芯的功率半导体装置
CN103824821B (zh) * 2014-03-11 2016-04-06 湖南进芯电子科技有限公司 一种塑料密闭封装的开关电源模块及其制备方法
US9967984B1 (en) 2015-01-14 2018-05-08 Vlt, Inc. Power adapter packaging
DE102015200868A1 (de) * 2015-01-20 2016-07-21 Zf Friedrichshafen Ag Steuerelektronik
US10264664B1 (en) 2015-06-04 2019-04-16 Vlt, Inc. Method of electrically interconnecting circuit assemblies
US10785871B1 (en) 2018-12-12 2020-09-22 Vlt, Inc. Panel molded electronic assemblies with integral terminals
US11336167B1 (en) 2016-04-05 2022-05-17 Vicor Corporation Delivering power to semiconductor loads
US9892999B2 (en) 2016-06-07 2018-02-13 Globalfoundries Inc. Producing wafer level packaging using leadframe strip and related device
US9953904B1 (en) * 2016-10-25 2018-04-24 Nxp Usa, Inc. Electronic component package with heatsink and multiple electronic components
CN107889425A (zh) * 2017-10-30 2018-04-06 惠州市德赛西威汽车电子股份有限公司 一种连接器散热结构
CN110120292B (zh) * 2018-02-05 2022-04-01 台达电子企业管理（上海）有限公司 磁性元件的散热结构及具有该散热结构的磁性元件
US11398417B2 (en) 2018-10-30 2022-07-26 Stmicroelectronics, Inc. Semiconductor package having die pad with cooling fins
US11515244B2 (en) * 2019-02-21 2022-11-29 Infineon Technologies Ag Clip frame assembly, semiconductor package having a lead frame and a clip frame, and method of manufacture
DE102019211109A1 (de) * 2019-07-25 2021-01-28 Siemens Aktiengesellschaft Verfahren und Entwärmungskörper-Anordnung zur Entwärmung von Halbleiterchips mit integrierten elektronischen Schaltungen für leistungselektronische Anwendungen

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JPH09321188A (ja) * 1996-05-24 1997-12-12 Nec Corp 半導体装置及びその実装方法
JP2002033433A (ja) * 2000-07-13 2002-01-31 Hitachi Ltd 半導体装置およびその製法
JP2002093847A (ja) * 2000-09-20 2002-03-29 Sanyo Electric Co Ltd 半導体装置および半導体モジュール
JP2003188324A (ja) * 2001-12-20 2003-07-04 Mitsubishi Electric Corp 放熱基材、放熱基材の製造方法、及び放熱基材を含む半導体装置
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011040507A (ja) * 2009-08-07 2011-02-24 Sumitomo Wiring Syst Ltd 回路装置
WO2018092185A1 (ja) * 2016-11-15 2018-05-24 三菱電機株式会社 半導体モジュール及び半導体装置
JPWO2018092185A1 (ja) * 2016-11-15 2019-04-11 三菱電機株式会社 半導体モジュール及び半導体装置
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KR102227212B1 (ko) 2019-06-24 2021-03-12 안상정 반도체 발광소자용 지지 기판을 제조하는 방법
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EP2005470A4 (en) 2010-12-22
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CN101416305A (zh) 2009-04-22
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US20100237479A1 (en) 2010-09-23
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