JP2009532874A5 - - Google Patents
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- Publication number
- JP2009532874A5 JP2009532874A5 JP2009503112A JP2009503112A JP2009532874A5 JP 2009532874 A5 JP2009532874 A5 JP 2009532874A5 JP 2009503112 A JP2009503112 A JP 2009503112A JP 2009503112 A JP2009503112 A JP 2009503112A JP 2009532874 A5 JP2009532874 A5 JP 2009532874A5
- Authority
- JP
- Japan
- Prior art keywords
- inter
- circuit
- barrier layer
- circuit trace
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004888 barrier function Effects 0.000 claims 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 claims 3
- 229910017052 cobalt Inorganic materials 0.000 claims 2
- 239000010941 cobalt Substances 0.000 claims 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims 2
- 239000000463 material Substances 0.000 claims 2
- 229910052759 nickel Inorganic materials 0.000 claims 2
- 239000003989 dielectric material Substances 0.000 claims 1
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/278,042 US7378339B2 (en) | 2006-03-30 | 2006-03-30 | Barrier for use in 3-D integration of circuits |
| PCT/US2007/062538 WO2007130731A2 (en) | 2006-03-30 | 2007-02-22 | Barrier for use in 3-d integration of circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2009532874A JP2009532874A (ja) | 2009-09-10 |
| JP2009532874A5 true JP2009532874A5 (enExample) | 2010-03-11 |
Family
ID=38559646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009503112A Pending JP2009532874A (ja) | 2006-03-30 | 2007-02-22 | 回路の三次元的な統合において用いられるバリヤ |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US7378339B2 (enExample) |
| JP (1) | JP2009532874A (enExample) |
| KR (1) | KR101352732B1 (enExample) |
| TW (1) | TWI416691B (enExample) |
| WO (1) | WO2007130731A2 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101030299B1 (ko) | 2008-08-08 | 2011-04-20 | 주식회사 동부하이텍 | 반도체 소자 및 그의 제조 방법 |
| JP5985136B2 (ja) | 2009-03-19 | 2016-09-06 | ソニー株式会社 | 半導体装置とその製造方法、及び電子機器 |
| US9406561B2 (en) * | 2009-04-20 | 2016-08-02 | International Business Machines Corporation | Three dimensional integrated circuit integration using dielectric bonding first and through via formation last |
| US9293366B2 (en) | 2010-04-28 | 2016-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate vias with improved connections |
| JP5577965B2 (ja) * | 2010-09-02 | 2014-08-27 | ソニー株式会社 | 半導体装置、および、その製造方法、電子機器 |
| US9142581B2 (en) | 2012-11-05 | 2015-09-22 | Omnivision Technologies, Inc. | Die seal ring for integrated circuit system with stacked device wafers |
| US10367031B2 (en) * | 2016-09-13 | 2019-07-30 | Imec Vzw | Sequential integration process |
| JP6905040B2 (ja) * | 2018-08-08 | 2021-07-21 | キヤノン株式会社 | 半導体デバイスの製造方法 |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4433845A1 (de) * | 1994-09-22 | 1996-03-28 | Fraunhofer Ges Forschung | Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung |
| US5756395A (en) * | 1995-08-18 | 1998-05-26 | Lsi Logic Corporation | Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structures |
| US6902987B1 (en) * | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
| JP2001291720A (ja) * | 2000-04-05 | 2001-10-19 | Hitachi Ltd | 半導体集積回路装置および半導体集積回路装置の製造方法 |
| KR20020010974A (ko) * | 2000-07-31 | 2002-02-07 | 박종섭 | 금속배선 형성 단계를 감소시킬 수 있는 강유전체 메모리소자 제조 방법 |
| US20030143853A1 (en) * | 2002-01-31 | 2003-07-31 | Celii Francis G. | FeRAM capacitor stack etch |
| US6656748B2 (en) * | 2002-01-31 | 2003-12-02 | Texas Instruments Incorporated | FeRAM capacitor post stack etch clean/repair |
| US6642081B1 (en) * | 2002-04-11 | 2003-11-04 | Robert Patti | Interlocking conductor method for bonding wafers to produce stacked integrated circuits |
| TWI225899B (en) * | 2003-02-18 | 2005-01-01 | Unitive Semiconductor Taiwan C | Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer |
| US20040262772A1 (en) * | 2003-06-30 | 2004-12-30 | Shriram Ramanathan | Methods for bonding wafers using a metal interlayer |
| US6924232B2 (en) * | 2003-08-27 | 2005-08-02 | Freescale Semiconductor, Inc. | Semiconductor process and composition for forming a barrier material overlying copper |
| US6867073B1 (en) * | 2003-10-21 | 2005-03-15 | Ziptronix, Inc. | Single mask via method and device |
| US7176128B2 (en) * | 2004-01-12 | 2007-02-13 | Infineon Technologies Ag | Method for fabrication of a contact structure |
| US7485968B2 (en) * | 2005-08-11 | 2009-02-03 | Ziptronix, Inc. | 3D IC method and device |
-
2006
- 2006-03-30 US US11/278,042 patent/US7378339B2/en active Active
-
2007
- 2007-02-22 KR KR1020087023823A patent/KR101352732B1/ko active Active
- 2007-02-22 WO PCT/US2007/062538 patent/WO2007130731A2/en not_active Ceased
- 2007-02-22 JP JP2009503112A patent/JP2009532874A/ja active Pending
- 2007-03-16 TW TW096109128A patent/TWI416691B/zh active
-
2008
- 2008-04-25 US US12/110,009 patent/US20080197497A1/en not_active Abandoned