KR101352732B1 - 회로의 3-ｄ 집적용 장벽 - Google Patents

회로의 3-ｄ 집적용 장벽 Download PDF

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KR101352732B1
KR101352732B1 KR1020087023823A KR20087023823A KR101352732B1 KR 101352732 B1 KR101352732 B1 KR 101352732B1 KR 1020087023823 A KR1020087023823 A KR 1020087023823A KR 20087023823 A KR20087023823 A KR 20087023823A KR 101352732 B1 KR101352732 B1 KR 101352732B1
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integrated circuit
inter
opening
circuit
trace
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KR20090004895A (ko
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스캇 케이. 포저
린 엠. 마이클슨
배러기즈 매튜
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프리스케일 세미컨덕터, 인크.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01042—Molybdenum [Mo]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
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    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020087023823A 2006-03-30 2007-02-22 회로의 3-ｄ 집적용 장벽 Active KR101352732B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/278,042 US7378339B2 (en) 2006-03-30 2006-03-30 Barrier for use in 3-D integration of circuits
US11/278,042 2006-03-30
PCT/US2007/062538 WO2007130731A2 (en) 2006-03-30 2007-02-22 Barrier for use in 3-d integration of circuits

Publications (2)

Publication Number Publication Date
KR20090004895A KR20090004895A (ko) 2009-01-12
KR101352732B1 true KR101352732B1 (ko) 2014-01-16

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KR1020087023823A Active KR101352732B1 (ko) 2006-03-30 2007-02-22 회로의 3-ｄ 집적용 장벽

Country Status (5)

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US (2) US7378339B2 (enExample)
JP (1) JP2009532874A (enExample)
KR (1) KR101352732B1 (enExample)
TW (1) TWI416691B (enExample)
WO (1) WO2007130731A2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101030299B1 (ko) 2008-08-08 2011-04-20 주식회사 동부하이텍 반도체 소자 및 그의 제조 방법
JP5985136B2 (ja) 2009-03-19 2016-09-06 ソニー株式会社 半導体装置とその製造方法、及び電子機器
US9406561B2 (en) * 2009-04-20 2016-08-02 International Business Machines Corporation Three dimensional integrated circuit integration using dielectric bonding first and through via formation last
US9293366B2 (en) 2010-04-28 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias with improved connections
JP5577965B2 (ja) * 2010-09-02 2014-08-27 ソニー株式会社 半導体装置、および、その製造方法、電子機器
US9142581B2 (en) 2012-11-05 2015-09-22 Omnivision Technologies, Inc. Die seal ring for integrated circuit system with stacked device wafers
US10367031B2 (en) * 2016-09-13 2019-07-30 Imec Vzw Sequential integration process
JP6905040B2 (ja) * 2018-08-08 2021-07-21 キヤノン株式会社 半導体デバイスの製造方法

Citations (3)

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Publication number Priority date Publication date Assignee Title
KR20020010974A (ko) * 2000-07-31 2002-02-07 박종섭 금속배선 형성 단계를 감소시킬 수 있는 강유전체 메모리소자 제조 방법
WO2005043584A2 (en) 2003-10-21 2005-05-12 Ziptronix, Inc. Single mask via method and device
KR20050105223A (ko) * 2003-02-18 2005-11-03 유니티브 일렉트로닉스 아이엔씨. 집적회로 기판의 선택적 범핑 방법 및 그 구조

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DE4433845A1 (de) * 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung
US5756395A (en) * 1995-08-18 1998-05-26 Lsi Logic Corporation Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structures
US6902987B1 (en) * 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
JP2001291720A (ja) * 2000-04-05 2001-10-19 Hitachi Ltd 半導体集積回路装置および半導体集積回路装置の製造方法
US20030143853A1 (en) * 2002-01-31 2003-07-31 Celii Francis G. FeRAM capacitor stack etch
US6656748B2 (en) * 2002-01-31 2003-12-02 Texas Instruments Incorporated FeRAM capacitor post stack etch clean/repair
US6642081B1 (en) * 2002-04-11 2003-11-04 Robert Patti Interlocking conductor method for bonding wafers to produce stacked integrated circuits
US20040262772A1 (en) * 2003-06-30 2004-12-30 Shriram Ramanathan Methods for bonding wafers using a metal interlayer
US6924232B2 (en) * 2003-08-27 2005-08-02 Freescale Semiconductor, Inc. Semiconductor process and composition for forming a barrier material overlying copper
US7176128B2 (en) * 2004-01-12 2007-02-13 Infineon Technologies Ag Method for fabrication of a contact structure
US7485968B2 (en) * 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020010974A (ko) * 2000-07-31 2002-02-07 박종섭 금속배선 형성 단계를 감소시킬 수 있는 강유전체 메모리소자 제조 방법
KR20050105223A (ko) * 2003-02-18 2005-11-03 유니티브 일렉트로닉스 아이엔씨. 집적회로 기판의 선택적 범핑 방법 및 그 구조
WO2005043584A2 (en) 2003-10-21 2005-05-12 Ziptronix, Inc. Single mask via method and device

Also Published As

Publication number Publication date
WO2007130731A3 (en) 2008-09-18
US20080197497A1 (en) 2008-08-21
TWI416691B (zh) 2013-11-21
JP2009532874A (ja) 2009-09-10
TW200742022A (en) 2007-11-01
US20070231950A1 (en) 2007-10-04
KR20090004895A (ko) 2009-01-12
WO2007130731A2 (en) 2007-11-15
US7378339B2 (en) 2008-05-27

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