JP2009515361A5 - - Google Patents

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Publication number
JP2009515361A5
JP2009515361A5 JP2008540029A JP2008540029A JP2009515361A5 JP 2009515361 A5 JP2009515361 A5 JP 2009515361A5 JP 2008540029 A JP2008540029 A JP 2008540029A JP 2008540029 A JP2008540029 A JP 2008540029A JP 2009515361 A5 JP2009515361 A5 JP 2009515361A5
Authority
JP
Japan
Prior art keywords
layer
photoresist layer
forming
opening
seed layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008540029A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009515361A (ja
Filing date
Publication date
Priority claimed from US11/267,975 external-priority patent/US7528069B2/en
Application filed filed Critical
Publication of JP2009515361A publication Critical patent/JP2009515361A/ja
Publication of JP2009515361A5 publication Critical patent/JP2009515361A5/ja
Pending legal-status Critical Current

Links

JP2008540029A 2005-11-07 2006-10-11 微細ピッチ相互接続及びその作製方法 Pending JP2009515361A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/267,975 US7528069B2 (en) 2005-11-07 2005-11-07 Fine pitch interconnect and method of making
PCT/US2006/040020 WO2007055863A2 (en) 2005-11-07 2006-10-11 Fine pitch interconnect and method of making

Publications (2)

Publication Number Publication Date
JP2009515361A JP2009515361A (ja) 2009-04-09
JP2009515361A5 true JP2009515361A5 (https=) 2009-10-22

Family

ID=38002924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008540029A Pending JP2009515361A (ja) 2005-11-07 2006-10-11 微細ピッチ相互接続及びその作製方法

Country Status (7)

Country Link
US (1) US7528069B2 (https=)
EP (1) EP1949426A4 (https=)
JP (1) JP2009515361A (https=)
KR (1) KR101452791B1 (https=)
CN (1) CN101305453B (https=)
TW (1) TWI408775B (https=)
WO (1) WO2007055863A2 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7750250B1 (en) * 2006-12-22 2010-07-06 Amkor Technology, Inc. Blind via capture pad structure
US20080272496A1 (en) 2007-05-02 2008-11-06 Starkey Laboratories, Inc. Planar interconnect structure for hybrid circuits
US9202713B2 (en) 2010-07-26 2015-12-01 Stats Chippac, Ltd. Semiconductor device and method of forming RDL over contact pad with high alignment tolerance or reduced interconnect pitch
KR101706517B1 (ko) * 2011-01-13 2017-02-13 타마랙 사이언티픽 컴퍼니 인코포레이티드 전도성 시드 레이어를 레이저 제거하는 방법 및 장치
US9171793B2 (en) 2011-05-26 2015-10-27 Hewlett-Packard Development Company, L.P. Semiconductor device having a trace comprises a beveled edge
US9520323B2 (en) * 2012-09-11 2016-12-13 Freescale Semiconductor, Inc. Microelectronic packages having trench vias and methods for the manufacture thereof
US9281293B2 (en) 2013-10-30 2016-03-08 Freescale Semiconductor Inc. Microelectronic packages having layered interconnect structures and methods for the manufacture thereof
US9312206B2 (en) 2014-03-04 2016-04-12 Freescale Semiconductor, Inc. Semiconductor package with thermal via and method for fabrication thereof
US9589909B1 (en) 2015-10-23 2017-03-07 Nxp Usa, Inc. Radio frequency and electromagnetic interference shielding in wafer level packaging using redistribution layers
US10276382B2 (en) * 2016-08-11 2019-04-30 Advanced Semiconductor Engineering, Inc. Semiconductor device packages and stacked package assemblies including high density interconnections

Family Cites Families (21)

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Publication number Priority date Publication date Assignee Title
US6753253B1 (en) * 1986-06-18 2004-06-22 Hitachi, Ltd. Method of making wiring and logic corrections on a semiconductor device by use of focused ion beams
US4714516A (en) 1986-09-26 1987-12-22 General Electric Company Method to produce via holes in polymer dielectrics for multiple electronic circuit chip packaging
JPH01176936U (https=) * 1988-05-31 1989-12-18
US5019997A (en) * 1989-06-05 1991-05-28 General Electric Company Adaptive lithography accommodation of tolerances in chip positioning in high density interconnection structures
US5933752A (en) * 1996-11-28 1999-08-03 Sony Corporation Method and apparatus for forming solder bumps for a semiconductor device
JP3335575B2 (ja) * 1997-06-06 2002-10-21 松下電器産業株式会社 半導体装置およびその製造方法
JP2004502296A (ja) 2000-06-26 2004-01-22 スリーエム　イノベイティブ　プロパティズ　カンパニー バイアのない印刷回路板
JP3440070B2 (ja) * 2000-07-13 2003-08-25 沖電気工業株式会社 ウェハー及びウェハーの製造方法
US6258705B1 (en) * 2000-08-21 2001-07-10 Siliconeware Precision Industries Co., Ltd. Method of forming circuit probing contact points on fine pitch peripheral bond pads on flip chip
US6506632B1 (en) 2002-02-15 2003-01-14 Unimicron Technology Corp. Method of forming IC package having downward-facing chip cavity
JP2003243394A (ja) * 2002-02-19 2003-08-29 Fuji Electric Co Ltd 半導体装置の製造方法
JP2003282698A (ja) 2002-03-22 2003-10-03 Sony Corp 半導体装置の製造方法および半導体装置
JP3551961B2 (ja) * 2002-04-10 2004-08-11 松下電器産業株式会社 半導体装置およびその製造方法
US7008872B2 (en) * 2002-05-03 2006-03-07 Intel Corporation Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures
TW200410377A (en) * 2002-12-02 2004-06-16 Shen Yu Nung Semiconductor chip package and the packaging method
DE10258081A1 (de) * 2002-12-11 2004-07-08 Infineon Technologies Ag Verfahren zum Herstellen einer Lötstopp-Anordnung
US7208825B2 (en) 2003-01-22 2007-04-24 Siliconware Precision Industries Co., Ltd. Stacked semiconductor packages
TWI241700B (en) 2003-01-22 2005-10-11 Siliconware Precision Industries Co Ltd Packaging assembly with integrated circuits redistribution routing semiconductor die and method for fabrication
JP2005129665A (ja) * 2003-10-22 2005-05-19 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US7087517B2 (en) 2003-12-24 2006-08-08 Intel Corporation Method to fabricate interconnect structures
KR100588904B1 (ko) 2003-12-31 2006-06-09 동부일렉트로닉스 주식회사 구리 배선 형성 방법

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