JP2009515348A5 - - Google Patents

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Publication number
JP2009515348A5
JP2009515348A5 JP2008539431A JP2008539431A JP2009515348A5 JP 2009515348 A5 JP2009515348 A5 JP 2009515348A5 JP 2008539431 A JP2008539431 A JP 2008539431A JP 2008539431 A JP2008539431 A JP 2008539431A JP 2009515348 A5 JP2009515348 A5 JP 2009515348A5
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JP
Japan
Prior art keywords
substrate
conductive
notch
passivation layer
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008539431A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009515348A (ja
Filing date
Publication date
Priority claimed from DE102005053494A external-priority patent/DE102005053494A1/de
Application filed filed Critical
Publication of JP2009515348A publication Critical patent/JP2009515348A/ja
Publication of JP2009515348A5 publication Critical patent/JP2009515348A5/ja
Pending legal-status Critical Current

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JP2008539431A 2005-11-09 2006-11-08 非導電性または半導電性の基板に導電性ブッシングを製作する方法 Pending JP2009515348A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005053494A DE102005053494A1 (de) 2005-11-09 2005-11-09 Verfahren zum Herstellen elektrisch leitender Durchführungen durch nicht- oder halbleitende Substrate
PCT/EP2006/068247 WO2007054521A1 (de) 2005-11-09 2006-11-08 Verfahren zum herstellen elektrisch leitender durchführungen durch nicht- oder halbleitende substrate

Publications (2)

Publication Number Publication Date
JP2009515348A JP2009515348A (ja) 2009-04-09
JP2009515348A5 true JP2009515348A5 (enExample) 2009-11-05

Family

ID=37651073

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008539431A Pending JP2009515348A (ja) 2005-11-09 2006-11-08 非導電性または半導電性の基板に導電性ブッシングを製作する方法

Country Status (5)

Country Link
US (1) US7781331B2 (enExample)
EP (1) EP1946367B1 (enExample)
JP (1) JP2009515348A (enExample)
DE (1) DE102005053494A1 (enExample)
WO (1) WO2007054521A1 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5298559B2 (ja) * 2007-06-29 2013-09-25 富士通株式会社 半導体装置及びその製造方法
JP2009021433A (ja) * 2007-07-12 2009-01-29 Fujikura Ltd 配線基板及びその製造方法
JP4713602B2 (ja) * 2008-02-21 2011-06-29 パナソニック株式会社 基板モジュールおよびその製造方法ならびに電子機器
US7973416B2 (en) * 2008-05-12 2011-07-05 Texas Instruments Incorporated Thru silicon enabled die stacking scheme
DE102008031836A1 (de) * 2008-07-05 2010-01-21 Deutsche Cell Gmbh Lotkontakt
WO2010013286A1 (ja) * 2008-07-28 2010-02-04 株式会社アドバンテスト 半導体装置および製造方法
JP2010251558A (ja) * 2009-04-16 2010-11-04 Toshiba Corp 固体撮像装置
FR2951017A1 (fr) * 2009-10-05 2011-04-08 St Microelectronics Crolles 2 Via de connexion electrique pour substrat de dispositif semi-conducteur
FR2951018A1 (fr) * 2009-10-05 2011-04-08 St Microelectronics Crolles 2 Via de connexion electrique pour substrat de dispositif semi-conducteur
JP2011187754A (ja) * 2010-03-10 2011-09-22 Toshiba Corp 固体撮像装置及びその製造方法
US8946083B2 (en) * 2011-06-24 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ formation of silicon and tantalum containing barrier
TW201401396A (zh) * 2012-05-25 2014-01-01 村田製作所股份有限公司 半導體裝置
US20150243597A1 (en) * 2014-02-25 2015-08-27 Inotera Memories, Inc. Semiconductor device capable of suppressing warping
US9601354B2 (en) * 2014-08-27 2017-03-21 Nxp Usa, Inc. Semiconductor manufacturing for forming bond pads and seal rings
CN111771303B (zh) 2017-12-26 2024-03-29 浦项控股股份有限公司 锂二次电池正极活性材料、其制备方法和包含它的锂二次电池
DE102023101372B3 (de) 2023-01-20 2024-03-28 Audi Aktiengesellschaft Elektronikanordnung, Kraftfahrzeug und Verfahren zum elektrischen Verbinden

Family Cites Families (18)

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US4097890A (en) * 1976-06-23 1978-06-27 Hewlett-Packard Company Low parasitic capacitance and resistance beamlead semiconductor component and method of manufacture
US4897708A (en) * 1986-07-17 1990-01-30 Laser Dynamics, Inc. Semiconductor wafer array
US4726879A (en) * 1986-09-08 1988-02-23 International Business Machines Corporation RIE process for etching silicon isolation trenches and polycides with vertical surfaces
JPH04174539A (ja) * 1990-11-07 1992-06-22 Oki Electric Ind Co Ltd 半導体装置
US5910687A (en) * 1997-01-24 1999-06-08 Chipscale, Inc. Wafer fabrication of die-bottom contacts for electronic devices
JP3724110B2 (ja) * 1997-04-24 2005-12-07 三菱電機株式会社 半導体装置の製造方法
DE69737262T2 (de) * 1997-11-26 2007-11-08 Stmicroelectronics S.R.L., Agrate Brianza Herstellungsverfahren für einen Vorder-Hinterseiten-Durchkontakt in mikro-integrierten Schaltungen
US6300670B1 (en) * 1999-07-26 2001-10-09 Stmicroelectronics, Inc. Backside bus vias
US6833079B1 (en) * 2000-02-17 2004-12-21 Applied Materials Inc. Method of etching a shaped cavity
JP3879816B2 (ja) * 2000-06-02 2007-02-14 セイコーエプソン株式会社 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器
JP2003332417A (ja) * 2002-05-08 2003-11-21 Toshiba Corp 半導体チップの製造方法
TWI229435B (en) 2002-06-18 2005-03-11 Sanyo Electric Co Manufacture of semiconductor device
US6903442B2 (en) * 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
JP2004095849A (ja) * 2002-08-30 2004-03-25 Fujikura Ltd 貫通電極付き半導体基板の製造方法、貫通電極付き半導体デバイスの製造方法
DE10244077B4 (de) * 2002-09-06 2007-03-15 INSTITUT FüR MIKROTECHNIK MAINZ GMBH Verfahren zur Herstellung von Halbleiterbauteilen mit Durchkontaktierung
JP4145301B2 (ja) * 2003-01-15 2008-09-03 富士通株式会社 半導体装置及び三次元実装半導体装置
TWI249767B (en) * 2004-02-17 2006-02-21 Sanyo Electric Co Method for making a semiconductor device
TWI303864B (en) * 2004-10-26 2008-12-01 Sanyo Electric Co Semiconductor device and method for making the same

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