JP2009514186A - ライン及びビア導体のための異なる材料を有するデュアル・ダマシン相互接続構造体 - Google Patents
ライン及びビア導体のための異なる材料を有するデュアル・ダマシン相互接続構造体 Download PDFInfo
- Publication number
- JP2009514186A JP2009514186A JP2006516136A JP2006516136A JP2009514186A JP 2009514186 A JP2009514186 A JP 2009514186A JP 2006516136 A JP2006516136 A JP 2006516136A JP 2006516136 A JP2006516136 A JP 2006516136A JP 2009514186 A JP2009514186 A JP 2009514186A
- Authority
- JP
- Japan
- Prior art keywords
- dielectric material
- layer
- opening
- conductor
- liner
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 title claims abstract description 195
- 239000000463 material Substances 0.000 title claims abstract description 48
- 230000009977 dual effect Effects 0.000 title abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 71
- 239000003989 dielectric material Substances 0.000 claims description 126
- 238000000151 deposition Methods 0.000 claims description 37
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 21
- 229910052721 tungsten Inorganic materials 0.000 claims description 21
- 239000010937 tungsten Substances 0.000 claims description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 17
- 239000010949 copper Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 15
- 229910052715 tantalum Inorganic materials 0.000 claims description 12
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 12
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 119
- 230000008021 deposition Effects 0.000 description 15
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 238000001020 plasma etching Methods 0.000 description 9
- 239000006117 anti-reflective coating Substances 0.000 description 7
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 6
- 229910052731 fluorine Inorganic materials 0.000 description 6
- 239000011737 fluorine Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 238000001459 lithography Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- FQNHWXHRAUXLFU-UHFFFAOYSA-N carbon monoxide;tungsten Chemical group [W].[O+]#[C-].[O+]#[C-].[O+]#[C-].[O+]#[C-].[O+]#[C-].[O+]#[C-] FQNHWXHRAUXLFU-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000002243 precursor Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000005382 thermal cycling Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 244000132059 Carica parviflora Species 0.000 description 1
- 235000014653 Carica parviflora Nutrition 0.000 description 1
- 229920004938 FOx® Polymers 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229920001577 copolymer Polymers 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 150000002170 ethers Chemical class 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 150000001282 organosilanes Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000412 polyarylene Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229920003051 synthetic elastomer Polymers 0.000 description 1
- 239000005061 synthetic rubber Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
【解決手段】 ライン導体に用いられるものとは異なる、ビア又はスタッドのための材料を用いるか、又はトレンチ・ライナに用いられるものとは異なる、ビア・ライナのための材料を用いるか、或いは該トレンチ・ライナのものと異なるビア・ライナ厚を有する、デュアル・ダマシンのバックエンド・オブ・ライン(back−end−of−line:BEOL)相互接続構造体を形成する方法が開示される。改善された機械的強度のために、ビアに厚い超硬合金を用いる一方で、トレンチに薄い超硬合金だけを用い、抵抗を低くすることが好ましい。
【選択図】 図1
Description
13:導体
16、17:ハードマスク層
18、20:ライナ
19:第1の部分(ビア又はスタッド)
19´19´´、21´、21´´:開口部
21:第2の部分(ライン導体)
Claims (24)
- 基板上に形成された相互接続構造体であって、前記構造体が、上面が誘電体材料の層の上面と同一平面にあるように少なくとも1つの第1の導体が埋め込まれた第1の誘電体材料の第1の層と、誘電体材料の前記第1の層の上に重なり、前記誘電体材料の層内に、上面が該誘電体材料の層の上面と同一平面にあるように少なくとも1つの第2の導体が埋め込まれた第2の誘電体材料の第2の層とを含み、前記第2の導体は少なくとも1つの第1の部分と前記第1の部分とは異なる材料で形成された少なくとも1つの第2の部分とを含み、該第1の部分が前記第1の導体と電気的に接触しており、前記第2の部分が該第1の部分の上に重なって該第1の部分と電気的に接触しており、該第2の部分は該第1の部分のものより大きい横方向範囲を有し、前記第2の部分の上面は、誘電体材料の前記第2の層の上面と同一平面にある、相互接続構造体。
- 前記第1の部分と前記第2の誘電体材料との間及び該第1の部分と前記第1の導体との間に配置された第1の導電性ライナと、前記第2の部分と該第2の誘電体材料との間及び該第2の部分と該第1の部分との間に配置された第2の導電性ライナとをさらに含み、前記第2のライナは前記第1のライナとは異なる材料で形成される、請求項1に記載の相互接続構造体。
- 誘電体材料の前記第2の層の上に重なるハードマスク層をさらに含み、前記第2の導体の前記第2の部分の上面は、前記ハードマスク層の上面と同一平面にある、請求項1又は請求項2に記載の相互接続構造体。
- 前記第2の誘電体材料が前記第1の誘電体材料と同じものである、請求項1、請求項2、又は請求項3に記載の相互接続構造体。
- 前記第2の誘電体材料が前記第1の誘電体材料とは異なるものである、請求項1乃至請求項4のいずれか1項に記載の相互接続構造体。
- 前記第2の部分が銅で形成され、前記第1の部分がタングステンで形成される、請求項1乃至請求項5のいずれか1項に記載の相互接続構造体。
- 前記第1のライナが、窒化チタン、タンタル、窒化タンタル、及びタングステンからなる群から選択される材料で形成され、前記第2のライナが、窒化タンタル及びタンタルからなる群から選択される材料で形成される、請求項2に記載の相互接続構造体。
- 前記第2のライナの厚さが前記第1のライナの厚さより薄い、請求項2に記載の相互接続構造体。
- 基板上に形成された相互接続構造体であって、前記構造体が、上面が誘電体材料の層の上面と同一平面にあるように少なくとも1つの第1の導体が埋め込まれた第1の誘電体材料の第1の層と、誘電体材料の前記第1の層の上に重なり、前記誘電体材料の層内に、上面が該誘電体材料の層の上面と同一平面にあるように少なくとも1つの第2の導体が埋め込まれた第2の誘電体材料の第2の層とを含み、前記第2の導体は少なくとも1つの第1の部分と少なくとも1つの第2の部分とを含み、前記第1の部分は前記第1の導体と電気的に接触しており、前記第2の部分が該第1の部分の上に重なって該第1の部分と電気的に接触しており、該第2の部分は該第1の部分のものより大きい横方向範囲を有し、前記第2の部分の上面は、誘電体材料の前記第2の層の上面と同一平面にあり、第1の導電性ライナが、該第1の部分と前記第2の誘電体材料との間及び該第1の部分と該第1の導体との間に配置され、厚さが前記第1のライナより薄い第2のライナが、該第2の部分と該第2の誘電体材料との間に配置される、相互接続構造体。
- 前記誘電体材料の第2の層の上に重なるハードマスク層をさらに含み、前記第2の導体の前記第2の部分の上面は、前記ハードマスク層の上面と同一平面にある、請求項9に記載の相互接続構造体。
- 前記第2の誘電体材料が前記第1の誘電体材料と同じものである、請求項9又は請求項10に記載の相互接続構造体。
- 前記第2の誘電体材料が前記第1の誘電体材料とは異なるものである、請求項9、請求項10、又は請求項11に記載の相互接続構造体。
- 前記第2の部分が銅で形成される、請求項9乃至請求項12のいずれか1項に記載の相互接続構造体。
- 前記第1のライナが、窒化チタン、タンタル、窒化タンタル、及びタングステンからなる群から選択される材料で構成され、前記第2のライナが、窒化タンタル及びタンタルからなる群から選択される材料で構成される、請求項9乃至請求項13のいずれか1項に記載の相互接続構造体。
- 前記第2の導体と前記第2の誘電体材料との間及び該第2の導体と前記第1の導体との間に配置される導電性ライナをさらに含む、請求項9乃至請求項14のいずれか1項に記載の相互接続構造体。
- 誘電体材料の前記第2の層の上に重なるハードマスク層をさらに含み、前記第2の導体の前記第2の部分の上面は、前記ハードマスク層の上面と同一平面にある上面を有する、請求項15に記載の相互接続構造体。
- 前記第2の誘電体材料が前記第1の誘電体材料と同じものである、請求項15に記載の相互接続構造体。
- 前記第2の誘電体材料が前記第1の誘電体材料とは異なるものである、請求項15に記載の相互接続構造体。
- 前記ライナが、窒化チタン、タンタル、窒化タンタル、及びタングステンからなる群から選択される材料から構成される、請求項15乃至請求項18のいずれか1項に記載の相互接続構造体。
- 上面が誘電体材料の層の上面と同一平面にあるように少なくとも1つの第1の導体が埋め込まれた第1の誘電体材料の第1の層を含む基板上に相互接続構造体を形成する方法であって、
前記方法が、誘電体材料の前記第1の層上に第2の誘電体材料の第2の層を堆積させるステップと、
誘電体材料の前記第2の層内に少なくとも1つの第1の開口部を形成して前記第1の導体を部分的に露出させるステップと、
前記第1の開口部を第1の導電性材料で充填するステップと、
前記第1の導電性材料の上部を除去するステップと、
誘電体材料の該第2の層内に、該第1の導電性材料の上に重なり、該第1の開口部のものより大きい横方向範囲を有する少なくとも1つの第2の開口部を形成するステップと、
前記第2の開口部を、前記第1の導電性材料とは異なる第2の導電性材料により、該第2の導電性材料の上面が誘電体材料の該第2の層の上面に対し同一平面にあるように充填するステップとを含む方法。 - 前記第1の開口部を前記第1の導電性材料で充填する前に、該第1の開口部の底部及び側壁上に第1の導電性ライナを堆積させるステップと、
前記第2の開口部を前記第2の導電性材料で充填する前に、該第2の開口部の底部及び側壁上に第2の導電性ライナを堆積させるステップとをさらに含む、請求項20に記載の方法。 - 上面が誘電体材料の層の上面と同一平面にあるように少なくとも1つの第1の導体が埋め込まれた第1の誘電体材料の第1の層を含む基板上に相互接続構造体を形成する方法であって、
前記方法が、誘電体材料の前記第1の層上に第2の誘電体材料の第2の層を堆積させるステップと、
誘電体材料の前記第2の層内に少なくとも1つの第1の開口部を形成し、前記第1の導体を部分的に露出させるステップと、
前記第1の開口部の底部及び側壁上に第1の導電性ライナを堆積させるステップと、
前記第1の開口部を犠牲材料で充填するステップと、
誘電体材料の該第2の層内に、該第1の開口部の上に重なり、該第1の開口部のものより大きい横方向範囲を有する少なくとも1つの第2の開口部を形成するステップと、
前記犠牲材料を除去するステップと、
前記第2の開口部の底部及び側壁上及び前記第1のライナ上に第2の導電性ライナを堆積させるステップと、
前記第2の開口部を、導電性材料により、前記第2の導体の上面が誘電体材料の該第2の層の上面に対し同一平面にあるように充填するステップとを含む方法。 - 上面が誘電体材料の層の上面と同一平面にあるように少なくとも1つの第1の導体が埋め込まれた第1の誘電体材料の第1の層を含む基板上に相互接続構造体を形成する方法であって、
前記方法が、誘電体材料の前記第1の層上に第2の誘電体材料の第2の層を堆積させるステップと、
誘電体材料の前記第2の層内に、誘電体材料の該第2の層を部分的に通って延びるが前記第1の導体を露出させない少なくとも1つの第1の開口部を形成するステップと、
誘電体材料の該第2の層内に、前記第1の開口部の上に重なり、該第1の開口部のものより大きい横方向範囲を有する少なくとも1つの第2の開口部を形成し、誘電体材料の残りを通して該第1の開口部を延ばして該第1の導体を露出させるステップと、
前記第1及び第2の開口部の底部及び側壁上に第1の導電性ライナを堆積させるステップと、該第1及び第2の開口部を第1の導電性材料で充填するステップと、
前記第2の開口部から前記第1の導電性材料及び前記第1のライナを除去するステップと、
前記第2の開口部の底部及び側壁上に第2の導電性ライナを堆積させるステップと、
前記第2の開口部を、前記第1の導電性材料とは異なる第2の導電性材料により、該第2の導電性材料の上面が誘電体材料の該第2の層の上面に対し同一平面にあるように充填するステップとを含む方法。 - 上面が誘電体材料の層の上面と同一平面にあるように少なくとも1つの第1の導体が埋め込まれた第1の誘電体材料の第1の層を含む基板上に相互接続構造体を形成する方法であって、
前記方法が、誘電体材料の前記第1の層上に第2の誘電体材料の第2の層を堆積させるステップと、
誘電体材料の前記第2の層内に、誘電体材料の該第2の層を部分的に通って延びるが前記第1の導体を露出させない少なくとも1つの第1の開口部を形成するステップと、
誘電体材料の該第2の層内に、前記第1の開口部の上に重なり、該第1の開口部のものより大きい横方向範囲を有する少なくとも1つの第2の開口部を形成し、誘電体材料の残りを通して該第1の開口部を延ばし、該第1の導体を露出させるステップと、
前記第1及び第2の開口部の底部及び側壁上に導電性ライナを堆積させるステップと、
前記第1及び第2の開口部を第1の導電性材料で充填するステップと、
前記第2の開口部から前記第1の導電性材料を除去するステップと、
前記第2の開口部を、該第1の導電性材料とは異なる第2の導電性材料により、該第2の導電性材料の上面が誘電体材料の該第2の層の上面に対し同一平面にあるように充填するステップとを含む方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/604,026 US6958540B2 (en) | 2003-06-23 | 2003-06-23 | Dual damascene interconnect structures having different materials for line and via conductors |
PCT/EP2004/051046 WO2004114395A2 (en) | 2003-06-23 | 2004-06-14 | Dual damascene interconnect structures having different materials for line and via conductors |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2009514186A true JP2009514186A (ja) | 2009-04-02 |
Family
ID=33539856
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006516136A Pending JP2009514186A (ja) | 2003-06-23 | 2004-06-14 | ライン及びビア導体のための異なる材料を有するデュアル・ダマシン相互接続構造体 |
Country Status (7)
Country | Link |
---|---|
US (3) | US6958540B2 (ja) |
EP (1) | EP1649510A2 (ja) |
JP (1) | JP2009514186A (ja) |
KR (1) | KR100772602B1 (ja) |
CN (1) | CN100405574C (ja) |
TW (2) | TWI345818B (ja) |
WO (1) | WO2004114395A2 (ja) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI242835B (en) * | 2003-08-29 | 2005-11-01 | Nanya Technology Corp | Structure of interconnects and fabricating method thereof |
US7169698B2 (en) * | 2004-01-14 | 2007-01-30 | International Business Machines Corporation | Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner |
KR100621630B1 (ko) * | 2004-08-25 | 2006-09-19 | 삼성전자주식회사 | 이종 금속을 이용하는 다마신 공정 |
US7352064B2 (en) * | 2004-11-04 | 2008-04-01 | International Business Machines Corporation | Multiple layer resist scheme implementing etch recipe particular to each layer |
US7651942B2 (en) * | 2005-08-15 | 2010-01-26 | Infineon Technologies Ag | Metal interconnect structure and method |
US7488679B2 (en) * | 2006-07-31 | 2009-02-10 | International Business Machines Corporation | Interconnect structure and process of making the same |
US7749894B2 (en) * | 2006-11-09 | 2010-07-06 | Chartered Semiconductor Manufacturing Ltd. | Integrated circuit processing system |
JP4506767B2 (ja) * | 2007-02-28 | 2010-07-21 | カシオ計算機株式会社 | 半導体装置の製造方法 |
US20080230907A1 (en) * | 2007-03-22 | 2008-09-25 | Chartered Semiconductor Manufacturing Ltd. | Integrated circuit system with carbon enhancement |
US7812461B2 (en) | 2007-03-27 | 2010-10-12 | Micron Technology, Inc. | Method and apparatus providing integrated circuit having redistribution layer with recessed connectors |
US7615484B2 (en) * | 2007-04-24 | 2009-11-10 | Chartered Semiconductor Manufacturing Ltd. | Integrated circuit manufacturing method using hard mask |
US7951414B2 (en) * | 2008-03-20 | 2011-05-31 | Micron Technology, Inc. | Methods of forming electrically conductive structures |
DE102011002769B4 (de) * | 2011-01-17 | 2013-03-21 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Halbleiterbauelement und Verfahren zur Herstellung einer Hybridkontaktstruktur mit Kontakten mit kleinem Aspektverhältnis in einem Halbleiterbauelement |
CN102437098A (zh) * | 2011-09-08 | 2012-05-02 | 上海华力微电子有限公司 | 一种降低接触孔电阻的接触孔形成方法 |
CN102437097A (zh) * | 2011-09-08 | 2012-05-02 | 上海华力微电子有限公司 | 一种新的接触孔的制造方法 |
CN102437099A (zh) * | 2011-09-08 | 2012-05-02 | 上海华力微电子有限公司 | 一种降低接触孔电阻的接触孔结构形成方法 |
US9252050B2 (en) | 2012-09-11 | 2016-02-02 | International Business Machines Corporation | Method to improve semiconductor surfaces and polishing |
US9312203B2 (en) * | 2013-01-02 | 2016-04-12 | Globalfoundries Inc. | Dual damascene structure with liner |
US9716035B2 (en) | 2014-06-20 | 2017-07-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Combination interconnect structure and methods of forming same |
US10727122B2 (en) | 2014-12-08 | 2020-07-28 | International Business Machines Corporation | Self-aligned via interconnect structures |
US9837309B2 (en) | 2015-11-19 | 2017-12-05 | International Business Machines Corporation | Semiconductor via structure with lower electrical resistance |
US9735051B2 (en) * | 2015-12-14 | 2017-08-15 | International Business Machines Corporation | Semiconductor device interconnect structures formed by metal reflow process |
KR102142795B1 (ko) * | 2016-02-02 | 2020-09-14 | 도쿄엘렉트론가부시키가이샤 | 선택적 증착을 이용한 금속 및 비아의 자기 정렬 |
KR20170110332A (ko) * | 2016-03-23 | 2017-10-11 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US10211153B2 (en) | 2016-08-30 | 2019-02-19 | International Business Machines Corporation | Low aspect ratio interconnect |
TWI625991B (zh) * | 2016-10-17 | 2018-06-01 | 南亞電路板股份有限公司 | 電路板結構與其製造方法 |
US10236206B2 (en) * | 2017-07-03 | 2019-03-19 | Globalfoundries Inc. | Interconnects with hybrid metallization |
CN107946332B (zh) * | 2017-11-22 | 2021-07-23 | 德淮半导体有限公司 | 半导体结构、cmos图像传感器及其制备方法 |
US10395986B1 (en) | 2018-05-30 | 2019-08-27 | International Business Machines Corporation | Fully aligned via employing selective metal deposition |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04162452A (ja) * | 1990-10-24 | 1992-06-05 | Nec Kyushu Ltd | 半導体装置の製造方法 |
JPH09306994A (ja) * | 1996-05-16 | 1997-11-28 | Lg Semicon Co Ltd | 半導体装置の配線形成方法 |
JP2001007200A (ja) * | 1999-06-21 | 2001-01-12 | Matsushita Electronics Industry Corp | 配線の形成方法 |
JP2001015510A (ja) * | 1999-06-28 | 2001-01-19 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2002368081A (ja) * | 2001-06-06 | 2002-12-20 | Sony Corp | 半導体装置の製造方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5739579A (en) * | 1992-06-29 | 1998-04-14 | Intel Corporation | Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections |
US5453575A (en) | 1993-02-01 | 1995-09-26 | Endosonics Corporation | Apparatus and method for detecting blood flow in intravascular ultrasonic imaging |
US6285082B1 (en) | 1995-01-03 | 2001-09-04 | International Business Machines Corporation | Soft metal conductor |
US5614765A (en) | 1995-06-07 | 1997-03-25 | Advanced Micro Devices, Inc. | Self aligned via dual damascene |
JP3228181B2 (ja) * | 1997-05-12 | 2001-11-12 | ヤマハ株式会社 | 平坦配線形成法 |
US6069068A (en) * | 1997-05-30 | 2000-05-30 | International Business Machines Corporation | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity |
US5821168A (en) * | 1997-07-16 | 1998-10-13 | Motorola, Inc. | Process for forming a semiconductor device |
US6127258A (en) | 1998-06-25 | 2000-10-03 | Motorola Inc. | Method for forming a semiconductor device |
US6297149B1 (en) * | 1999-10-05 | 2001-10-02 | International Business Machines Corporation | Methods for forming metal interconnects |
US6383821B1 (en) | 1999-10-29 | 2002-05-07 | Conexant Systems, Inc. | Semiconductor device and process |
JP2001319928A (ja) | 2000-05-08 | 2001-11-16 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US6403456B1 (en) * | 2000-08-22 | 2002-06-11 | Advanced Micro Devices, Inc. | T or T/Y gate formation using trim etch processing |
US20020086519A1 (en) * | 2000-12-29 | 2002-07-04 | Houston Theodore W. | Stacked vias and method |
US6537913B2 (en) * | 2001-06-29 | 2003-03-25 | Intel Corporation | Method of making a semiconductor device with aluminum capped copper interconnect pads |
TW522479B (en) | 2001-12-07 | 2003-03-01 | Taiwan Semiconductor Mfg | Method of forming dual-damascene |
US20040108217A1 (en) * | 2002-12-05 | 2004-06-10 | Dubin Valery M. | Methods for forming copper interconnect structures by co-plating of noble metals and structures formed thereby |
US7060619B2 (en) * | 2003-03-04 | 2006-06-13 | Infineon Technologies Ag | Reduction of the shear stress in copper via's in organic interlayer dielectric material |
US20040222527A1 (en) * | 2003-05-06 | 2004-11-11 | Dostalik William W. | Dual damascene pattern liner |
-
2003
- 2003-06-23 US US10/604,026 patent/US6958540B2/en not_active Expired - Lifetime
-
2004
- 2004-06-14 CN CNB2004800149580A patent/CN100405574C/zh not_active Expired - Fee Related
- 2004-06-14 JP JP2006516136A patent/JP2009514186A/ja active Pending
- 2004-06-14 WO PCT/EP2004/051046 patent/WO2004114395A2/en active Search and Examination
- 2004-06-14 EP EP04741743A patent/EP1649510A2/en not_active Ceased
- 2004-06-14 KR KR1020057022397A patent/KR100772602B1/ko not_active IP Right Cessation
- 2004-06-18 TW TW093117825A patent/TWI345818B/zh not_active IP Right Cessation
- 2004-06-18 TW TW098105172A patent/TW200931593A/zh unknown
-
2005
- 2005-07-05 US US11/174,985 patent/US7300867B2/en not_active Expired - Fee Related
-
2007
- 2007-08-30 US US11/847,657 patent/US7704876B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04162452A (ja) * | 1990-10-24 | 1992-06-05 | Nec Kyushu Ltd | 半導体装置の製造方法 |
JPH09306994A (ja) * | 1996-05-16 | 1997-11-28 | Lg Semicon Co Ltd | 半導体装置の配線形成方法 |
JP2001007200A (ja) * | 1999-06-21 | 2001-01-12 | Matsushita Electronics Industry Corp | 配線の形成方法 |
JP2001015510A (ja) * | 1999-06-28 | 2001-01-19 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2002368081A (ja) * | 2001-06-06 | 2002-12-20 | Sony Corp | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20060025149A (ko) | 2006-03-20 |
US20040262764A1 (en) | 2004-12-30 |
US20080026566A1 (en) | 2008-01-31 |
WO2004114395A2 (en) | 2004-12-29 |
TW200512874A (en) | 2005-04-01 |
CN100405574C (zh) | 2008-07-23 |
EP1649510A2 (en) | 2006-04-26 |
US7704876B2 (en) | 2010-04-27 |
KR100772602B1 (ko) | 2007-11-02 |
TWI345818B (en) | 2011-07-21 |
US20050245068A1 (en) | 2005-11-03 |
US6958540B2 (en) | 2005-10-25 |
WO2004114395A3 (en) | 2005-02-10 |
US7300867B2 (en) | 2007-11-27 |
TW200931593A (en) | 2009-07-16 |
CN1799137A (zh) | 2006-07-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7704876B2 (en) | Dual damascene interconnect structures having different materials for line and via conductors | |
US6838355B1 (en) | Damascene interconnect structures including etchback for low-k dielectric materials | |
JP4162241B2 (ja) | 犠牲無機ポリマ金属間誘電体を用いたダマシン配線およびビア・ライナ | |
KR100389174B1 (ko) | 금속 캐패시터 및 이의 형성 방법 | |
US6924228B2 (en) | Method of forming a via contact structure using a dual damascene technique | |
US8138082B2 (en) | Method for forming metal interconnects in a dielectric material | |
KR100702549B1 (ko) | 반도체 인터커넥트 구조 상의 금속층 증착 방법 | |
JP3870031B2 (ja) | キャパシタ構造およびその製造方法 | |
US7662722B2 (en) | Air gap under on-chip passive device | |
US6011311A (en) | Multilevel interconnect structure for integrated circuits | |
US20080203579A1 (en) | Sacrificial metal spacer dual damascene | |
US20020064941A1 (en) | Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene | |
US20070155165A1 (en) | Methods for forming damascene wiring structures having line and plug conductors formed from different materials | |
JP4084513B2 (ja) | デュアルダマシン(dualdamascene)の製造方法 | |
US7071100B2 (en) | Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process | |
US20120142188A1 (en) | Anchored damascene structures | |
JP2009224816A (ja) | 半導体装置のマスク層および二重ダマシーン相互接続構造 | |
JP2008004939A (ja) | デバイス、方法(mimキャパシタおよびその製造方法) | |
US6406992B1 (en) | Fabrication method for a dual damascene structure | |
US6660619B1 (en) | Dual damascene metal interconnect structure with dielectric studs | |
US20030170978A1 (en) | Method of fabricating a dual damascene structure on a semiconductor substrate | |
US6403471B1 (en) | Method of forming a dual damascene structure including smoothing the top part of a via | |
US6417106B1 (en) | Underlayer liner for copper damascene in low k dielectric | |
US7662711B2 (en) | Method of forming dual damascene pattern | |
US8048799B2 (en) | Method for forming copper wiring in semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100427 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110322 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110406 Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20110406 |
|
RD12 | Notification of acceptance of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7432 Effective date: 20110406 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20110408 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20110526 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110915 Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20110915 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20110922 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20111028 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20120702 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20121113 |
|
RD14 | Notification of resignation of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7434 Effective date: 20121113 |