JP2009289849A - 配線基板及び半導体パッケージ - Google Patents
配線基板及び半導体パッケージ Download PDFInfo
- Publication number
- JP2009289849A JP2009289849A JP2008138910A JP2008138910A JP2009289849A JP 2009289849 A JP2009289849 A JP 2009289849A JP 2008138910 A JP2008138910 A JP 2008138910A JP 2008138910 A JP2008138910 A JP 2008138910A JP 2009289849 A JP2009289849 A JP 2009289849A
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- Prior art keywords
- layer
- wiring
- filler
- solder resist
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 166
- 239000000945 filler Substances 0.000 claims abstract description 143
- 229910000679 solder Inorganic materials 0.000 claims abstract description 114
- 239000002245 particle Substances 0.000 claims abstract description 84
- 239000000758 substrate Substances 0.000 claims description 68
- 238000013508 migration Methods 0.000 abstract description 19
- 230000005012 migration Effects 0.000 abstract description 19
- 239000010410 layer Substances 0.000 description 351
- 238000000034 method Methods 0.000 description 39
- 229910052751 metal Inorganic materials 0.000 description 38
- 239000002184 metal Substances 0.000 description 38
- 238000004519 manufacturing process Methods 0.000 description 31
- 238000011156 evaluation Methods 0.000 description 30
- 239000011347 resin Substances 0.000 description 28
- 229920005989 resin Polymers 0.000 description 28
- 238000007747 plating Methods 0.000 description 26
- 239000011342 resin composition Substances 0.000 description 26
- 239000010949 copper Substances 0.000 description 25
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- 229910045601 alloy Inorganic materials 0.000 description 8
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 6
- 229910021536 Zeolite Inorganic materials 0.000 description 6
- AOWKSNWVBZGMTJ-UHFFFAOYSA-N calcium titanate Chemical compound [Ca+2].[O-][Ti]([O-])=O AOWKSNWVBZGMTJ-UHFFFAOYSA-N 0.000 description 6
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 6
- HNPSIPDUKPIQMN-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Al]O[Al]=O HNPSIPDUKPIQMN-UHFFFAOYSA-N 0.000 description 6
- 150000003949 imides Chemical class 0.000 description 6
- 150000002484 inorganic compounds Chemical class 0.000 description 6
- 229910010272 inorganic material Inorganic materials 0.000 description 6
- 238000009413 insulation Methods 0.000 description 6
- 150000002894 organic compounds Chemical class 0.000 description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 6
- 230000002265 prevention Effects 0.000 description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000002904 solvent Substances 0.000 description 6
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 6
- 239000010457 zeolite Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000005457 optimization Methods 0.000 description 5
- 238000005476 soldering Methods 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000007864 aqueous solution Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
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- 238000007788 roughening Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
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- 229960003280 cupric chloride Drugs 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
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- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
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- 239000002356 single layer Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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Abstract
【解決手段】絶縁層と、前記絶縁層上に形成された配線と、前記配線の少なくとも一部を覆うように前記絶縁層上に形成されたソルダーレジスト層と、を有し、前記ソルダーレジスト層が複数の層から構成されている配線基板であって、前記複数の層は粒径の異なるフィラーを含有し、前記複数の層を構成する最内層の層厚は前記配線の層厚よりも厚く、前記最内層に含有される前記フィラーの粒径は、隣接する前記配線同士の最短間隔よりも小さいことを特徴とする。
【選択図】図5
Description
第1の実施の形態では、本発明を多層配線層(ビルドアップ配線層)を有する配線基板に適用する例を示す。図4は、本発明の第1の実施の形態に係るビルドアップ配線層を有する配線基板を例示する断面図である。図4を参照するに、配線基板10は、第1絶縁層13aと、第2絶縁層13bと、第3絶縁層13cと、配線14aと、配線14bと、配線14cと、配線14dと、ソルダーレジスト層15と、金属層16とを有するビルドアップ配線層を備えた配線基板である。
第2の実施の形態では、本発明をビルドアップ配線層を有する配線基板を備えた半導体パッケージに適用する例を示す。図21は、本発明の第2の実施の形態に係る半導体パッケージを例示する断面図である。図21において、図4と同一部品については、同一符号を付し、その説明は省略する場合がある。図21を参照するに、半導体パッケージ20は、図4に示す配線基板10と、半導体チップ21と、アンダーフィル樹脂22とを有する。配線基板10の金属層16上には、はんだペースト塗布等によりプレソルダ23が形成されている。金属層16とプレソルダ23とは、電気的に接続されている。
第3の実施の形態では、本発明を平面視した状態で半導体チップと略同じ大きさとされたチップサイズの半導体パッケージ(所謂チップサイズパッケージ:CSP)に適用する例を示す。図23は、本発明の第3の実施の形態に係る半導体パッケージを例示する断面図である。図23を参照するに、半導体パッケージ30は、半導体チップ31と、内部接続端子32と、絶縁層33と、配線34と、ソルダーレジスト層36と、外部接続端子37とを有する。
11 支持体
12 レジスト膜
12x,15x,36x 開口部
13a 第1絶縁層
13b 第2絶縁層
13c 第3絶縁層
13x 第1ビアホール
13y 第2ビアホール
13z 第3ビアホール
14a,14b,14c,14d,14e,34 配線
15,36 ソルダーレジスト層
15a,36a 内層
15b,36b 外層
16,46 金属層
17a,17b,17c,17d,38a,38b フィラー
18 表面めっき層
19 パッド本体
20,30 半導体パッケージ
21,31 半導体チップ
21a ボール状端子
22 アンダーフィル樹脂
23 プレソルダ
32 内部接続端子
32a,33a 上面
33 絶縁層
37 外部接続端子
41,51 半導体基板
42 半導体集積回路
43 電極パッド
44 保護膜
A 半導体パッケージ形成領域
B スクライブ領域
C 基板切断位置
H1 高さ
P3,P5 最短間隔
T1,T2,T3,T4,T5,T6 厚さ
φ2,φ3,φ4,φ5 粒径
Claims (10)
- 絶縁層と、前記絶縁層上に形成された配線と、前記配線の少なくとも一部を覆うように前記絶縁層上に形成されたソルダーレジスト層と、を有し、
前記ソルダーレジスト層が複数の層から構成されている配線基板であって、
前記複数の層は粒径の異なるフィラーを含有し、前記複数の層を構成する最内層の層厚は前記配線の層厚よりも厚く、前記最内層に含有される前記フィラーの粒径は、隣接する前記配線同士の最短間隔よりも小さいことを特徴とする配線基板。 - 前記最内層に含有される前記フィラーの粒径は、それ以外の層に含有される前記フィラーの粒径よりも小さいことを特徴とする請求項1記載の配線基板。
- 前記最内層に含有される前記フィラーの量は、それ以外の層に含有される前記フィラーの量と略同一であることを特徴とする請求項1又は2記載の配線基板。
- 前記フィラーの二次凝集物は、前記最内層に含有されていないことを特徴とする請求項1乃至3の何れか一項記載の配線基板。
- 絶縁層と、前記絶縁層上に形成された配線と、前記配線の少なくとも一部を覆うように前記絶縁層上に形成されたソルダーレジスト層と、を有し、
前記ソルダーレジスト層が複数の層から構成されている配線基板であって、
前記複数の層を構成する最内層の層厚は前記配線の層厚よりも厚く、前記最内層はフィラーを含有していないことを特徴とする配線基板。 - 請求項1乃至5の何れか一項記載の配線基板と、半導体チップとを有する半導体パッケージであって、
前記半導体チップは、前記配線基板の前記配線の前記ソルダーレジストから露出する部分と電気的に接続されていることを特徴とする半導体パッケージ。 - 絶縁層と、前記絶縁層上に形成された配線と、前記配線の少なくとも一部を覆うように前記絶縁層上に形成されたソルダーレジスト層と、を有し、
前記ソルダーレジスト層が複数の層から構成されている半導体パッケージであって、
前記複数の層は粒径の異なるフィラーを含有し、前記複数の層を構成する最内層の層厚は前記配線の層厚よりも厚く、前記最内層に含有される前記フィラーの粒径は、隣接する前記配線同士の最短間隔よりも小さいことを特徴とする半導体パッケージ。 - 前記最内層に含有される前記フィラーの粒径は、それ以外の層に含有される前記フィラーの粒径よりも小さいことを特徴とする請求項7記載の半導体パッケージ。
- 前記最内層に含有される前記フィラーの量は、それ以外の層に含有される前記フィラーの量と略同一であることを特徴とする請求項7又は8記載の半導体パッケージ。
- 前記フィラーの二次凝集物は、前記最内層に含有されていないことを特徴とする請求項7乃至9の何れか一項記載の半導体パッケージ。
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JP5121574B2 (ja) * | 2008-05-28 | 2013-01-16 | 新光電気工業株式会社 | 配線基板及び半導体パッケージ |
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JP2000031628A (ja) * | 1998-07-16 | 2000-01-28 | Ibiden Co Ltd | プリント配線板及びその製造方法 |
JP2000294921A (ja) * | 1999-04-01 | 2000-10-20 | Victor Co Of Japan Ltd | プリンス基板及びその製造方法 |
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JP7452040B2 (ja) | 2020-01-30 | 2024-03-19 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
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