JP2009239318A5 - - Google Patents

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Publication number
JP2009239318A5
JP2009239318A5 JP2009171214A JP2009171214A JP2009239318A5 JP 2009239318 A5 JP2009239318 A5 JP 2009239318A5 JP 2009171214 A JP2009171214 A JP 2009171214A JP 2009171214 A JP2009171214 A JP 2009171214A JP 2009239318 A5 JP2009239318 A5 JP 2009239318A5
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JP
Japan
Prior art keywords
traces
pair
trace
layout
ball
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2009171214A
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English (en)
Japanese (ja)
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JP5254899B2 (ja
JP2009239318A (ja
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Application filed filed Critical
Publication of JP2009239318A publication Critical patent/JP2009239318A/ja
Publication of JP2009239318A5 publication Critical patent/JP2009239318A5/ja
Application granted granted Critical
Publication of JP5254899B2 publication Critical patent/JP5254899B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2009171214A 1998-02-19 2009-07-22 高性能ボールグリッドアレイパッケージの最適回路設計レイアウト Expired - Lifetime JP5254899B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US7529098P 1998-02-19 1998-02-19
US075290 1998-02-19

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP11041955A Division JPH11317471A (ja) 1998-02-19 1999-02-19 高性能ボ―ルグリッドアレイパッケ―ジの最適回路設計レイアウト

Publications (3)

Publication Number Publication Date
JP2009239318A JP2009239318A (ja) 2009-10-15
JP2009239318A5 true JP2009239318A5 (enExample) 2012-02-16
JP5254899B2 JP5254899B2 (ja) 2013-08-07

Family

ID=22124740

Family Applications (2)

Application Number Title Priority Date Filing Date
JP11041955A Pending JPH11317471A (ja) 1998-02-19 1999-02-19 高性能ボ―ルグリッドアレイパッケ―ジの最適回路設計レイアウト
JP2009171214A Expired - Lifetime JP5254899B2 (ja) 1998-02-19 2009-07-22 高性能ボールグリッドアレイパッケージの最適回路設計レイアウト

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP11041955A Pending JPH11317471A (ja) 1998-02-19 1999-02-19 高性能ボ―ルグリッドアレイパッケ―ジの最適回路設計レイアウト

Country Status (2)

Country Link
US (3) US6215184B1 (enExample)
JP (2) JPH11317471A (enExample)

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JP3610262B2 (ja) * 1999-07-22 2005-01-12 新光電気工業株式会社 多層回路基板及び半導体装置
JP2002170844A (ja) 2000-12-04 2002-06-14 Oki Electric Ind Co Ltd 半導体装置
TW200408091A (en) * 2001-11-13 2004-05-16 Koninkl Philips Electronics Nv Device for shielding transmission lines from ground or power supply
US6686666B2 (en) 2002-05-16 2004-02-03 Intel Corporation Breaking out signals from an integrated circuit footprint
US20040091027A1 (en) * 2002-11-07 2004-05-13 Booth Bradley J. System, method and device for autonegotiation
US7720135B2 (en) * 2002-11-07 2010-05-18 Intel Corporation System, method and device for autonegotiation
US6933596B2 (en) * 2003-07-01 2005-08-23 Northrop Grumman Corporation Ultra wideband BGA
US7038319B2 (en) * 2003-08-20 2006-05-02 International Business Machines Corporation Apparatus and method to reduce signal cross-talk
US7057115B2 (en) * 2004-01-26 2006-06-06 Litton Systems, Inc. Multilayered circuit board for high-speed, differential signals
JP4425044B2 (ja) * 2004-04-13 2010-03-03 新光電気工業株式会社 半導体パッケージにおける自動配線方法および装置ならびに自動識別装置
US20060185895A1 (en) * 2005-02-24 2006-08-24 Navinchandra Kalidas Universal pattern of contact pads for semiconductor reflow interconnections
CN100574552C (zh) * 2005-08-12 2009-12-23 鸿富锦精密工业（深圳）有限公司 印刷电路板
US8370704B2 (en) 2009-03-09 2013-02-05 Intel Corporation Cable interconnection techniques
US8307265B2 (en) * 2009-03-09 2012-11-06 Intel Corporation Interconnection techniques
US8379710B2 (en) * 2009-03-10 2013-02-19 Intel Corporation Transmitter control in communication systems
KR20130125036A (ko) * 2012-05-08 2013-11-18 삼성전자주식회사 시스템 온 칩, 이의 동작 방법, 및 이를 포함하는 시스템
WO2014038542A1 (ja) * 2012-09-07 2014-03-13 株式会社フジクラ 配線基板
WO2015027180A1 (en) * 2013-08-23 2015-02-26 Molex Incorporated Led module
KR102245132B1 (ko) 2014-05-14 2021-04-28 삼성전자 주식회사 트레이스를 가지는 인쇄회로기판 및 볼 그리드 어레이 패키지
KR102339899B1 (ko) 2014-12-12 2021-12-15 삼성전자주식회사 반도체 패키지, 모듈 기판 및 이를 포함하는 반도체 패키지 모듈

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JP2736107B2 (ja) * 1989-03-14 1998-04-02 株式会社東芝 信号配線基板
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US5729894A (en) * 1992-07-21 1998-03-24 Lsi Logic Corporation Method of assembling ball bump grid array semiconductor packages
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JP3362545B2 (ja) * 1995-03-09 2003-01-07 ソニー株式会社 半導体装置の製造方法
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US5686764A (en) * 1996-03-20 1997-11-11 Lsi Logic Corporation Flip chip package with reduced number of package layers
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JP2976917B2 (ja) * 1997-03-31 1999-11-10 日本電気株式会社 半導体装置
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US6075710A (en) * 1998-02-11 2000-06-13 Express Packaging Systems, Inc. Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips

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