JP2013526770A5 - - Google Patents

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Publication number
JP2013526770A5
JP2013526770A5 JP2013509319A JP2013509319A JP2013526770A5 JP 2013526770 A5 JP2013526770 A5 JP 2013526770A5 JP 2013509319 A JP2013509319 A JP 2013509319A JP 2013509319 A JP2013509319 A JP 2013509319A JP 2013526770 A5 JP2013526770 A5 JP 2013526770A5
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JP
Japan
Prior art keywords
substrate
semiconductor die
semiconductor
semiconductor device
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2013509319A
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English (en)
Japanese (ja)
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JP2013526770A (ja
Filing date
Publication date
Priority claimed from US12/776,302 external-priority patent/US8288849B2/en
Application filed filed Critical
Publication of JP2013526770A publication Critical patent/JP2013526770A/ja
Publication of JP2013526770A5 publication Critical patent/JP2013526770A5/ja
Pending legal-status Critical Current

Links

JP2013509319A 2010-05-07 2011-05-09 ワイドバスメモリ及びシリアルメモリをチップ・スケール・パッケージフットプリント内のプロセッサに取り付けるための方法 Pending JP2013526770A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/776,302 2010-05-07
US12/776,302 US8288849B2 (en) 2010-05-07 2010-05-07 Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint
PCT/US2011/035753 WO2011140552A2 (en) 2010-05-07 2011-05-09 Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint

Publications (2)

Publication Number Publication Date
JP2013526770A JP2013526770A (ja) 2013-06-24
JP2013526770A5 true JP2013526770A5 (enExample) 2014-05-29

Family

ID=44901410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013509319A Pending JP2013526770A (ja) 2010-05-07 2011-05-09 ワイドバスメモリ及びシリアルメモリをチップ・スケール・パッケージフットプリント内のプロセッサに取り付けるための方法

Country Status (4)

Country Link
US (2) US8288849B2 (enExample)
JP (1) JP2013526770A (enExample)
CN (1) CN102859686B (enExample)
WO (1) WO2011140552A2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8227295B2 (en) * 2008-10-16 2012-07-24 Texas Instruments Incorporated IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
US8288849B2 (en) * 2010-05-07 2012-10-16 Texas Instruments Incorporated Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint
US8384430B2 (en) * 2010-08-16 2013-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. RC delay detectors with high sensitivity for through substrate vias
KR101818507B1 (ko) * 2012-01-11 2018-01-15 삼성전자 주식회사 반도체 패키지
US9230932B2 (en) 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
US9515036B2 (en) 2012-04-20 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for solder connections
US9847284B2 (en) * 2013-01-29 2017-12-19 Apple Inc. Stacked wafer DDR package
US9721852B2 (en) * 2014-01-21 2017-08-01 International Business Machines Corporation Semiconductor TSV device package to which other semiconductor device package can be later attached
US10128205B2 (en) * 2014-03-06 2018-11-13 Intel Corporation Embedded die flip-chip package assembly
KR102108608B1 (ko) * 2014-07-11 2020-05-07 인텔 코포레이션 스케일링가능한 패키지 아키텍처 및 연관된 기법과 구성
CN107534027B (zh) * 2015-06-15 2021-08-17 索尼公司 半导体装置、电子设备和制造方法
US11152333B2 (en) * 2018-10-19 2021-10-19 Micron Technology, Inc. Semiconductor device packages with enhanced heat management and related systems

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7217994B2 (en) * 2004-12-01 2007-05-15 Kyocera Wireless Corp. Stack package for high density integrated circuits
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
US7569918B2 (en) 2006-05-01 2009-08-04 Texas Instruments Incorporated Semiconductor package-on-package system including integrated passive components
US20080258286A1 (en) 2007-04-23 2008-10-23 Texas Instruments Incorporated High Input/Output, Low Profile Package-On-Package Semiconductor System
US20080258285A1 (en) 2007-04-23 2008-10-23 Texas Instruments Incorporated Simplified Substrates for Semiconductor Devices in Package-on-Package Products
JP5222509B2 (ja) * 2007-09-12 2013-06-26 ルネサスエレクトロニクス株式会社 半導体装置
US7547630B2 (en) 2007-09-26 2009-06-16 Texas Instruments Incorporated Method for stacking semiconductor chips
US8049320B2 (en) 2008-02-19 2011-11-01 Texas Instruments Incorporated Integrated circuit stacked package precursors and stacked packaged devices and systems therefrom
US7851346B2 (en) * 2008-07-21 2010-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding metallurgy for three-dimensional interconnect
JP2010056139A (ja) * 2008-08-26 2010-03-11 Toshiba Corp 積層型半導体装置
KR101479509B1 (ko) * 2008-08-29 2015-01-08 삼성전자주식회사 반도체 패키지
US8227295B2 (en) 2008-10-16 2012-07-24 Texas Instruments Incorporated IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
US8183579B2 (en) * 2010-03-02 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. LED flip-chip package structure with dummy bumps
US8218334B2 (en) * 2010-03-09 2012-07-10 Oracle America, Inc. Multi-chip module with multi-level interposer
US8288849B2 (en) * 2010-05-07 2012-10-16 Texas Instruments Incorporated Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint

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