CN102859686B - 用于在芯片级封装占用面积内将宽总线存储器及串行存储器附接到处理器的方法 - Google Patents

用于在芯片级封装占用面积内将宽总线存储器及串行存储器附接到处理器的方法 Download PDF

Info

Publication number
CN102859686B
CN102859686B CN201180021433.XA CN201180021433A CN102859686B CN 102859686 B CN102859686 B CN 102859686B CN 201180021433 A CN201180021433 A CN 201180021433A CN 102859686 B CN102859686 B CN 102859686B
Authority
CN
China
Prior art keywords
substrate
semiconductor die
front surface
die
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201180021433.XA
Other languages
English (en)
Chinese (zh)
Other versions
CN102859686A (zh
Inventor
库尔特·瓦赫特勒
玛格丽特·罗丝·西蒙斯-马修斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN102859686A publication Critical patent/CN102859686A/zh
Application granted granted Critical
Publication of CN102859686B publication Critical patent/CN102859686B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Microcomputers (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
CN201180021433.XA 2010-05-07 2011-05-09 用于在芯片级封装占用面积内将宽总线存储器及串行存储器附接到处理器的方法 Active CN102859686B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/776,302 US8288849B2 (en) 2010-05-07 2010-05-07 Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint
US12/776,302 2010-05-07
PCT/US2011/035753 WO2011140552A2 (en) 2010-05-07 2011-05-09 Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint

Publications (2)

Publication Number Publication Date
CN102859686A CN102859686A (zh) 2013-01-02
CN102859686B true CN102859686B (zh) 2015-08-19

Family

ID=44901410

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201180021433.XA Active CN102859686B (zh) 2010-05-07 2011-05-09 用于在芯片级封装占用面积内将宽总线存储器及串行存储器附接到处理器的方法

Country Status (4)

Country Link
US (2) US8288849B2 (enExample)
JP (1) JP2013526770A (enExample)
CN (1) CN102859686B (enExample)
WO (1) WO2011140552A2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8227295B2 (en) * 2008-10-16 2012-07-24 Texas Instruments Incorporated IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
US8288849B2 (en) * 2010-05-07 2012-10-16 Texas Instruments Incorporated Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint
US8384430B2 (en) * 2010-08-16 2013-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. RC delay detectors with high sensitivity for through substrate vias
KR101818507B1 (ko) * 2012-01-11 2018-01-15 삼성전자 주식회사 반도체 패키지
US9230932B2 (en) 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
US9515036B2 (en) 2012-04-20 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for solder connections
US9847284B2 (en) * 2013-01-29 2017-12-19 Apple Inc. Stacked wafer DDR package
US9721852B2 (en) 2014-01-21 2017-08-01 International Business Machines Corporation Semiconductor TSV device package to which other semiconductor device package can be later attached
US10128205B2 (en) * 2014-03-06 2018-11-13 Intel Corporation Embedded die flip-chip package assembly
US9793244B2 (en) 2014-07-11 2017-10-17 Intel Corporation Scalable package architecture and associated techniques and configurations
WO2016203967A1 (ja) * 2015-06-15 2016-12-22 ソニー株式会社 半導体装置、電子機器、並びに製造方法
US11152333B2 (en) * 2018-10-19 2021-10-19 Micron Technology, Inc. Semiconductor device packages with enhanced heat management and related systems

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009026224A2 (en) * 2007-08-16 2009-02-26 Texas Instruments Incorporated High input/output, low profile package-on-package semiconductor system

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7217994B2 (en) * 2004-12-01 2007-05-15 Kyocera Wireless Corp. Stack package for high density integrated circuits
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
US7569918B2 (en) 2006-05-01 2009-08-04 Texas Instruments Incorporated Semiconductor package-on-package system including integrated passive components
US20080258285A1 (en) 2007-04-23 2008-10-23 Texas Instruments Incorporated Simplified Substrates for Semiconductor Devices in Package-on-Package Products
JP5222509B2 (ja) * 2007-09-12 2013-06-26 ルネサスエレクトロニクス株式会社 半導体装置
US7547630B2 (en) 2007-09-26 2009-06-16 Texas Instruments Incorporated Method for stacking semiconductor chips
US8049320B2 (en) 2008-02-19 2011-11-01 Texas Instruments Incorporated Integrated circuit stacked package precursors and stacked packaged devices and systems therefrom
US7851346B2 (en) * 2008-07-21 2010-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding metallurgy for three-dimensional interconnect
JP2010056139A (ja) * 2008-08-26 2010-03-11 Toshiba Corp 積層型半導体装置
KR101479509B1 (ko) * 2008-08-29 2015-01-08 삼성전자주식회사 반도체 패키지
US8227295B2 (en) 2008-10-16 2012-07-24 Texas Instruments Incorporated IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
US8183579B2 (en) * 2010-03-02 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. LED flip-chip package structure with dummy bumps
US8218334B2 (en) * 2010-03-09 2012-07-10 Oracle America, Inc. Multi-chip module with multi-level interposer
US8288849B2 (en) * 2010-05-07 2012-10-16 Texas Instruments Incorporated Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009026224A2 (en) * 2007-08-16 2009-02-26 Texas Instruments Incorporated High input/output, low profile package-on-package semiconductor system

Also Published As

Publication number Publication date
US8288849B2 (en) 2012-10-16
JP2013526770A (ja) 2013-06-24
US20120225523A1 (en) 2012-09-06
WO2011140552A3 (en) 2012-03-01
US20110272814A1 (en) 2011-11-10
CN102859686A (zh) 2013-01-02
WO2011140552A2 (en) 2011-11-10
US8597978B2 (en) 2013-12-03

Similar Documents

Publication Publication Date Title
CN102859686A (zh) 用于在芯片级封装占用面积内将宽总线存储器及串行存储器附接到处理器的方法
KR102708730B1 (ko) 브리지 다이를 포함한 반도체 패키지
CN104064551B (zh) 一种芯片堆叠封装结构和电子设备
CN102867800B (zh) 将功能芯片连接至封装件以形成层叠封装件
CN109585430B (zh) 包含双面重布层之堆栈半导体封装组件
CN102456677B (zh) 球栅阵列封装结构及其制造方法
CN104253115B (zh) 用于半导体封装中减小的管芯到管芯间隔的底部填充材料流控制
JP5763121B2 (ja) シリコン貫通ビアのブリッジする相互接続
US8159057B2 (en) Semiconductor device and manufacturing method therefor
US9391025B2 (en) Reliable microstrip routing for electronics components
CN105097750A (zh) 封装结构及其制法
CN105489566A (zh) 半导体封装结构
CN105428334A (zh) 半导体封装结构
TW201351579A (zh) 高密度立體封裝
CN103208487A (zh) 用于较薄堆叠封装件结构的方法和装置
CN105261608A (zh) 高密度芯片到芯片连接
CN110620100A (zh) 一种适用于高密度高功率的封装结构及制造方法
CN102290395B (zh) 堆叠封装
US20150115437A1 (en) Universal encapsulation substrate, encapsulation structure and encapsulation method
US20210167038A1 (en) Dual in-line memory module
CN113939911B (zh) 一种芯片以及集成芯片
CN100392849C (zh) 封装体及封装体模块
CN221783207U (zh) 一种芯片封装结构及电子设备
CN115132595A (zh) 集成封装方法和集成封装结构
CN102446881B (zh) 一种通用封装基板及其封装方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant