JP2013526770A - ワイドバスメモリ及びシリアルメモリをチップ・スケール・パッケージフットプリント内のプロセッサに取り付けるための方法 - Google Patents

ワイドバスメモリ及びシリアルメモリをチップ・スケール・パッケージフットプリント内のプロセッサに取り付けるための方法 Download PDF

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Publication number
JP2013526770A
JP2013526770A JP2013509319A JP2013509319A JP2013526770A JP 2013526770 A JP2013526770 A JP 2013526770A JP 2013509319 A JP2013509319 A JP 2013509319A JP 2013509319 A JP2013509319 A JP 2013509319A JP 2013526770 A JP2013526770 A JP 2013526770A
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substrate
semiconductor die
die
semiconductor
electrically connected
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Japanese (ja)
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JP2013526770A5 (enExample
Inventor
ワクトゥラ カート
ローズ シモンズ マシューズ マーガレット
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日本テキサス・インスツルメンツ株式会社
テキサス インスツルメンツ インコーポレイテッド
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Publication of JP2013526770A publication Critical patent/JP2013526770A/ja
Publication of JP2013526770A5 publication Critical patent/JP2013526770A5/ja
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
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    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
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    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Microcomputers (AREA)
  • Dram (AREA)
JP2013509319A 2010-05-07 2011-05-09 ワイドバスメモリ及びシリアルメモリをチップ・スケール・パッケージフットプリント内のプロセッサに取り付けるための方法 Pending JP2013526770A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/776,302 US8288849B2 (en) 2010-05-07 2010-05-07 Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint
US12/776,302 2010-05-07
PCT/US2011/035753 WO2011140552A2 (en) 2010-05-07 2011-05-09 Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint

Publications (2)

Publication Number Publication Date
JP2013526770A true JP2013526770A (ja) 2013-06-24
JP2013526770A5 JP2013526770A5 (enExample) 2014-05-29

Family

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Application Number Title Priority Date Filing Date
JP2013509319A Pending JP2013526770A (ja) 2010-05-07 2011-05-09 ワイドバスメモリ及びシリアルメモリをチップ・スケール・パッケージフットプリント内のプロセッサに取り付けるための方法

Country Status (4)

Country Link
US (2) US8288849B2 (enExample)
JP (1) JP2013526770A (enExample)
CN (1) CN102859686B (enExample)
WO (1) WO2011140552A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016526306A (ja) * 2014-07-11 2016-09-01 インテル コーポレイション スケーラブルパッケージアーキテクチャ並びに関連する技法及び構造

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8227295B2 (en) * 2008-10-16 2012-07-24 Texas Instruments Incorporated IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
US8288849B2 (en) * 2010-05-07 2012-10-16 Texas Instruments Incorporated Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint
US8384430B2 (en) * 2010-08-16 2013-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. RC delay detectors with high sensitivity for through substrate vias
KR101818507B1 (ko) * 2012-01-11 2018-01-15 삼성전자 주식회사 반도체 패키지
US9230932B2 (en) 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
US9515036B2 (en) 2012-04-20 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for solder connections
US9847284B2 (en) 2013-01-29 2017-12-19 Apple Inc. Stacked wafer DDR package
US9721852B2 (en) 2014-01-21 2017-08-01 International Business Machines Corporation Semiconductor TSV device package to which other semiconductor device package can be later attached
US10128205B2 (en) * 2014-03-06 2018-11-13 Intel Corporation Embedded die flip-chip package assembly
CN107534027B (zh) * 2015-06-15 2021-08-17 索尼公司 半导体装置、电子设备和制造方法
US11152333B2 (en) * 2018-10-19 2021-10-19 Micron Technology, Inc. Semiconductor device packages with enhanced heat management and related systems

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090079067A1 (en) * 2007-09-26 2009-03-26 Texas Instruments Incorporated Method for Stacking Semiconductor Chips
JP2009070965A (ja) * 2007-09-12 2009-04-02 Renesas Technology Corp 半導体装置
US20100052132A1 (en) * 2008-08-29 2010-03-04 Samsung Electronics Co., Ltd. Semiconductor package
JP2010056139A (ja) * 2008-08-26 2010-03-11 Toshiba Corp 積層型半導体装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7217994B2 (en) * 2004-12-01 2007-05-15 Kyocera Wireless Corp. Stack package for high density integrated circuits
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
US7569918B2 (en) 2006-05-01 2009-08-04 Texas Instruments Incorporated Semiconductor package-on-package system including integrated passive components
US20080258286A1 (en) 2007-04-23 2008-10-23 Texas Instruments Incorporated High Input/Output, Low Profile Package-On-Package Semiconductor System
US20080258285A1 (en) 2007-04-23 2008-10-23 Texas Instruments Incorporated Simplified Substrates for Semiconductor Devices in Package-on-Package Products
US8049320B2 (en) 2008-02-19 2011-11-01 Texas Instruments Incorporated Integrated circuit stacked package precursors and stacked packaged devices and systems therefrom
US7851346B2 (en) * 2008-07-21 2010-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding metallurgy for three-dimensional interconnect
US8227295B2 (en) 2008-10-16 2012-07-24 Texas Instruments Incorporated IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
US8183579B2 (en) * 2010-03-02 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. LED flip-chip package structure with dummy bumps
US8218334B2 (en) * 2010-03-09 2012-07-10 Oracle America, Inc. Multi-chip module with multi-level interposer
US8288849B2 (en) * 2010-05-07 2012-10-16 Texas Instruments Incorporated Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009070965A (ja) * 2007-09-12 2009-04-02 Renesas Technology Corp 半導体装置
US20090079067A1 (en) * 2007-09-26 2009-03-26 Texas Instruments Incorporated Method for Stacking Semiconductor Chips
JP2010056139A (ja) * 2008-08-26 2010-03-11 Toshiba Corp 積層型半導体装置
US20100052132A1 (en) * 2008-08-29 2010-03-04 Samsung Electronics Co., Ltd. Semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016526306A (ja) * 2014-07-11 2016-09-01 インテル コーポレイション スケーラブルパッケージアーキテクチャ並びに関連する技法及び構造

Also Published As

Publication number Publication date
CN102859686B (zh) 2015-08-19
US8288849B2 (en) 2012-10-16
WO2011140552A3 (en) 2012-03-01
CN102859686A (zh) 2013-01-02
US20120225523A1 (en) 2012-09-06
WO2011140552A2 (en) 2011-11-10
US8597978B2 (en) 2013-12-03
US20110272814A1 (en) 2011-11-10

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