TWI457764B - 處理器／快取裝配件 - Google Patents

處理器／快取裝配件 Download PDF

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TWI457764B
TWI457764B TW098101922A TW98101922A TWI457764B TW I457764 B TWI457764 B TW I457764B TW 098101922 A TW098101922 A TW 098101922A TW 98101922 A TW98101922 A TW 98101922A TW I457764 B TWI457764 B TW I457764B
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cache
processor
die
contact pads
semiconductor die
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TW098101922A
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TW200939035A (en
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Perry H Pelley
Michael B Mcshane
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Freescale Semiconductor Inc
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Description

處理器/快取裝配件
此揭示內容一般係關於半導體，且更明確而言，係關於存在於具有多晶粒之半導體封裝中之處理操作速度。
本申請案已於2008年2月5日在美國申請為專利申請案第12/026,325號。
熟知將兩個或兩個以上的半導體封裝於彼此頂部堆疊用以減小底面積區域。其他人還提出將兩個或兩個以上的半導體晶粒於彼此頂部堆疊。已提出各種解決方式用於處理與在將兩個分離半導體彼此緊密接近放置時所產生的額外熱量相關聯之問題。該等半導體之大小及其功能繼續限制堆疊半導體之實際使用以及有效率進行電連接至緊密接近之多個半導體的能力。
商用資料處理系統一般利用多個核心或處理單元。例如，在桌上型處理環境中普遍藉由在同時處理資訊之一方法中分割功能來有效率地使用雙核心處理器。在授予Periaman等人的美國專利7,279,795中，揭示一種堆疊晶粒半導體，其中一晶粒係多核心處理器晶粒而且一第二晶粒含有用於該多個核心之一共用記憶體。該共用記憶體必須因此製造地較大以最小化對一主晶片外記憶體的記憶體存取之數目。與其中每一處理器核心具有位於相同晶粒上之一記憶體及一記憶體控制的單晶片實施方案相比，此一組態之有效資料通信頻寬會降低。在多處理核心系統中有效率解決資料通信頻寬與該等大小或封裝底面積問題兩者仍較麻煩。
圖1中解說一處理器晶粒9的一主表面，該處理器晶粒9具有以具有列及行之一陣列提供的複數個個別且單獨處理單元11至35。在其他形式中，可將該等處理單元11至35以除處理單元之列及行外之幾何組態的一陣列來放置。該等處理單元11至35之每一者係各種資料處理器之任一類型。例如，該等處理單元11至35之每一者可為一中央處理單元(CPU)、一數位信號處理器、一圖形特定處理器、一微控制器單元(MCU)、一通信處理器或任何其他處理單元類型。另外，該等處理單元11至35可為相同類型的處理單元或可在橫跨該處理器晶粒9在處理單元類型之間變動。在所解說形式中，存在5列，隨著每一處理單元列具有5行。應瞭解，所解說具體實施例僅係範例性的且可實施處理單元之X列及Y行之任何數目，其中X與Y係2或更大的整數。在一形式中，僅實施四個處理單元。此外，應瞭解，該等處理單元11至35之實體大小或佈局區域不必如圖1中所解說般地均勻。當實施功能性不同類型之處理單元時，由每一處理單元所消耗的電路面積可能不同。另外，應瞭解，雖然為該等處理單元11至35之每一者提供矩形形狀，但可實施其他幾何形狀。在所解說形式中，應瞭解，在該等處理單元11至35之每一者之間提供一些實體分離及互連。然而，提供此隔離所要求之晶粒面積的數量係總晶粒之一有限數量且因此並未加以解說。此外，應注意，處理器晶粒9之實質上所有區域係用於該等處理單元11至35之專用區域而且此具體實施例因此在大小上極有效率。
圖2中解說另一具體實施例，其中一處理器晶粒10之一主表面具有處理單元11至35以及作為該等處理單元11至35之周邊的一外部連接區域38兩者。具有一外部邊緣的該等處理單元11至35之每一者藉由該外部連接區域38來鄰接。此因此將為處理單元11至15、16、20、21、25、26、30以及31至35。在該外部連接區域38內係複數個外部接觸墊44，其係放置於預定位置用於自該等處理單元11至35之外部提供連接。為進一步參考，還分別將處理單元21至25標記P1至P5。在一形式中，一外部接觸墊40係用於線接合連接至該處理器晶粒10外之電路的一矩形墊。類似地，一外部接觸墊42係用於放置一導電凸塊(諸如一焊料凸塊)的一圓形墊。在此具體實施例中，該外部連接區域38係該晶粒10之一區域，其中從晶粒10之外部進行電連接。在該外部連接區域38內的該等接觸墊下面係導電佈線(自圖2之視圖不可見)，其將該等接觸墊連接至該晶粒10內的預定電路。該等接觸墊傳達功率、資料、控制信號及位址信號並提供獲得對該處理器晶粒10之外部存取的一方式。
圖3中解說一快取晶粒45之俯視圖，其具有複數個快取單元或快取單元之一陣列。該等快取單元46至70之每一者係一半導體快取(即，記憶體)。該等快取單元46至70之每一者係任一類型的快取記憶體。例如，該等快取單元46至70之每一者可為靜態隨機存取記憶體(SRAM)、快閃記憶體、磁阻隨機存取記憶體(MRAM)、動態隨機存取記憶體(DRAM)或任何其他記憶體類型。該等快取單元46至70可為相同類型的記憶體單元或可變動。在所解說形式中，存在5列，而每一快取單元列具有5行。應注意，所解說具體實施例具有與處理單元相同數目之列及行的快取單元，使得每一處理單元係與一獨佔且單獨快取單元相關。
此外，應瞭解，該等快取單元46至70之實體大小或佈局區域意在與圖1之處理器晶粒9或圖2之處理器晶粒10之一預定之不同處理單元相關。在此相關中，處理器晶粒9或處理器晶粒10之每一快取單元係用於連接至快取晶粒45之快取單元之一特定指定者。因此，在一第一晶粒中之每一處理單元具有於一第二晶粒中之一專用快取單元。每一快取單元消耗的電路面積可能因此不同。另外，應瞭解，雖然為該等快取單元46至70之每一者提供矩形，但可實施其他幾何形狀。在所解說形式中，應瞭解，在該等快取單元46至70之每一者之間提供一些實體分離及互連。然而，提供此隔離之晶粒面積所要求的數量係總晶粒之一有限數量，且因此並未加以解說。此外，應注意，處理器晶粒9之實質上所有區域係用於該等快取單元46至70之專用區域，而且此具體實施例因此在大小上亦極有效率。在圖3解說中，至每一快取單元的各種互連並未顯示於所示的俯視圖中。
為進一步瞭解與圖3之快取單元之每一者相關聯的連接，在圖4中解說分別沿圖2及圖3之每一者之線4-4截取之處理器晶粒10與快取晶粒45的斷面。如圖4中解說之處理器晶粒10與快取晶粒45之連接形成一多處理器/快取裝配件，其中該處理器晶粒9係直接連接至該快取晶粒45。在所解說形式中，該處理器晶粒10以一預定對準與該快取晶粒45對準，以形成指定為處理器/快取73、處理器/快取74、處理器/快取75、處理器/快取76及處理器/快取77之區域。在此等區域之每一者內，一處理器與一對應快取毗連。每一區域毗連或同延意指其具有實質上相同或一致邊界。藉由四個多導體匯流排來連接此等處理器/快取組合之每一者，如圖4中解說。所使用匯流排之數目隨應用而異，而且其他形式可使用比所解說的更少或更多的匯流排。快取單元56係經由一資料匯流排80、一位址匯流排82、一控制匯流排84以及一狀態匯流排86來連接至該處理單元21。該資料匯流排80係雙向的。該位址匯流排82係單向的，該處理單元21以其直接提供記憶體位址至該快取單元56。該控制匯流排84亦係單向的，其中該處理單元21提供控制資訊至該快取單元56，以控制對該快取單元56的記憶體存取。在一些形式中，該控制匯流排84可為雙向的。該狀態匯流排86亦係單向的，其中該快取單元56提供狀態資訊至該處理單元21。可使用各種實體結構之任一者來實體實施本文中討論之該等匯流排。在一形式中，導電凸塊(諸如焊料凸塊)可用於在該處理器晶粒10直接附接於該快取晶粒45時形成處理器單元/快取單元連接。在其他形式中，可在處理器晶粒10及快取晶粒45之每一者的表面上使用導電接觸墊，使得在其連接於一起時，將一處理單元直接連接至一快取單元。該等接觸因此在方向上係直接且垂直的。在此形式中，該等直接接觸係較短的，且因此近似一多層單晶粒之電氣性質。因此，最小化與在一處理器與一快取之間之連接器相關聯的電容及電感，從而改良包括速度、面積及功率之效能參數。
在多處理器/快取裝配件72之解說形式中，該處理器晶粒10寬於該快取晶粒45延伸用以曝露該外部連接區域38。如圖4中解說，提供該外部接觸墊40用於將來接觸該多處理器/快取裝配件。可藉由導電凸塊、線接合或其他互連方法來接觸該外部接觸墊40。
圖5中解說另一具體實施例，其中提供一插入物90用於分離該處理器晶粒9與該快取晶粒45以形成一多處理器/快取裝配件88。在此形式中，採用實質上相同寬度來實施該處理器晶粒9與該快取晶粒45。外部接觸該多處理器/快取裝配件88係藉由在至少一側上延伸該插入物90超出該處理器晶粒9與該快取晶粒45之寬度來進行。在圖5中，將插入物90向右延伸。將一外部接點92與一外部接點94定位於插入物90之曝露部分的對立側上。電接觸該插入物90之該等曝露接點可藉由各種方法(諸如以在插入物90之兩側上的接點周圍擬合的一夾子接觸來連接該插入物90)來進行。或者，可使用具有一凹陷之一插座。在又另一形式中，該插入物90可擬合至在一基板內的一接觸孔。在其他形式中，可對該插入物90之外部接點進行線接合或焊球連接。該插入物90可由各種材料之任一者形成。在一形式中，插入物90係矽。其他適當材料包括導熱陶瓷或撓性有機膜。該插入物90具有複數個導孔或開口用於放置導電材料以實施該等匯流排(諸如資料匯流排80、位址匯流排82、控制匯流排84以及狀態匯流排86)的導體。由於該快取晶粒45相對於該處理器晶粒9之實體佈局，該快取單元60或C5係直接連接至該處理單元25或P5。類似地，單元C4係直接連接至單元P4。單元C3係直接連接至單元P3而單元C2係直接連接至單元P2。單元C1係直接連接至單元P1。
應瞭解，有效散熱技術可用於與圖4與5之多處理器/快取裝配件88連接。例如，在該處理器晶粒9與10以及該快取晶粒45之曝露側或表面上，可放置各種熱移除結構及材料。此外，取決於用於該插入物90之材料，可獲得一些熱遠離該多處理核心及快取而傳遞。
圖6中解說圖5之處理器/快取74之一部分的一細節。詳細解說經由定位於該兩晶粒之間的該插入物90自該快取晶粒45至該處理器晶粒9的連接。該快取單元57覆蓋並連接至圖6中之處理單元22。僅該快取單元57與該處理單元22之每一者的一小部分顯示為藉由該處理器/快取74之兩部分之間的一斷裂來指定。在左側解說一位址導體而且在右側解說一資料導體。該位址導體使用在該插入物90中的一開口或導孔，其識別為導電導孔96。應瞭解，導電導孔96之開口係使用導電材料(諸如金屬或其他電導體)來加以填充。一導電凸塊98覆蓋該導電導孔96並藉由接觸一接觸墊102而接觸該快取單元57。一導電凸塊99覆蓋該導電導孔96並經由一接觸墊103來接觸該處理單元22。附接至該插入物90係用於載送電源信號以及其他信號(諸如資料)的各種導電跡線。該資料導體係藉由在該插入物90中的一開口或導孔(其係識別為導電導孔97)來加以實施。任一導電材料均可用於實施該導電導孔。一導電凸塊100覆蓋該導電導孔97並藉由接觸一接觸墊104而接觸該快取單元57。用於外部連接之一資料跡線114位於該導電導孔97下面並經由在一接觸墊105處的一導電凸塊101來接觸該處理單元22。應瞭解並注意，一空隙可能存在於該插入物90與鄰近該等導電凸塊連接的該快取晶粒45與該處理器晶粒9之每一者之間。在其他形式中，可一起充分壓縮該兩晶粒以使得空隙極小。在另一具體實施例中，一填充材料(未顯示)可用於填充該空隙。在所解說形式中，一極直接且較短電氣路徑因此存在於一第一晶粒上的一處理單元與用於在該第一晶粒上面或下面之一第二晶粒上的此處理單元之一相關專用快取之間。本文中提供的該等結構實施一多處理器陣列，其具有有效率連接的用於每一處理器的一特定、專用快取記憶體。在一快取記憶體與一相關處理器之間的直接接觸准許關於類型、大小、速度等訂製快取而非具有一共同快取記憶體用於可能採用不同參數操作的多處理器。快取記憶體速度與一相關聯處理器之適當匹配准許有效率地訂製一處理系統。應進一步瞭解，在另一實施方案中，在該快取晶粒45上的該等快取記憶體的一或多者可實施為一雙埠快取記憶體並分別具有第一與第二輸入埠，其係連接至處理器晶粒10上的兩不同處理單元。還應注意，該等導電凸塊98至101可最初形成在該插入物90上而非該處理器晶粒10與該快取晶粒45上。該等導電凸塊最初放置在該插入物90上避免與凸塊接合該晶粒相關聯之潛在良率問題。與一晶粒之凸塊接合程序相關聯之任何缺陷比凸塊接合一插入物係更昂貴。
本文使用的術語"匯流排"用以引用複數個信號或導體，其可用以傳送一個或多個各種類型的資訊，諸如資料、位址、控制或狀態。如本文討論的導體可參考單一導體、複數個導體、單向導體或雙向導體加以解說或說明。然而，不同具體實施例可變動該等導體之實施方案。例如，可使用單獨單向導體，而非雙向導體且反之亦然。並且，複數個導體可使用串列或以一時間多工化方式傳送多個信號的單一導體來取代。同樣地，可將載送多個信號的單一導體分成載送此等信號之子集的各種不同導體。因此，傳送信號可有許多選擇。
至此應瞭解，在一多處理器(多核心)陣列與一快取記憶體之間提供一高頻寬通信系統。在實體匹配快取記憶體之間使用一插入物之垂直連接，由於較短及直接的連接而提供有效面積使用及高頻寬。在一晶粒內之一陣列中的每一處理器或核心具有一覆蓋快取記憶體，其係實體對準以在一堆疊晶粒組合中直接連接。本文中說明的各種具體實施例採用每一相關處理器/快取記憶體對之一對一對準來實施一對匹配半導體晶粒。由此，可實體相鄰或緊接著一處理器核心來實施極大型快取記憶體而不增加該處理器之晶粒大小。藉由實施大型儲存快取記憶體，降低對使用一外部主系統記憶體之要求，並且顯著改良系統效率。因此導致對主記憶體之較低頻寬要求。
在一形式中，本文中提供一處理器/快取裝配件，其具有一第一半導體晶粒，該第一半導體晶粒具有一處理單元陣列。該處理單元陣列的每一處理單元具有一組處理器接觸墊。該等處理器接觸墊係在該第一半導體晶粒之一表面上的導電墊。每一組處理器接觸墊係獨特於該處理單元陣列之所有其他處理單元之該組處理器接觸墊。每一組處理器接觸墊包括用於位址信號之一第一處理器接觸墊子集，以及用於資料信號之一第二處理器接觸墊子集。一第二半導體晶粒具有一快取單元陣列。該快取單元陣列之每一快取單元具有一組快取接觸墊。該等快取接觸墊係在該第二半導體晶粒外之一表面上的導電墊。每一組快取接觸墊係獨特於該快取單元陣列之所有其他快取單元之該組快取接觸墊。每一組外部接觸墊包括用於位址信號之一第一快取接觸墊子集，以及用於資料信號之一第二快取接觸墊子集。每一快取單元之該第一快取接觸墊子集係連接至該等處理器單元之一獨特者之該第一處理器接觸墊子集。每一快取單元之該第二快取接觸墊子集係連接至其第一快取接觸墊子集所連接之該處理器單元之該第二處理器接觸墊子集。在一形式中，該第一半導體晶粒具有一主表面，且該等處理器接觸墊係在該第一半導體晶粒之該主表面上。該第二半導體晶粒具有一主表面，且該等快取接觸墊係在該第二半導體晶粒之該主表面上。該第一半導體晶粒之該主表面面向該第二半導體晶粒之該主表面。在又另一形式中，該等處理器接觸墊係透過導電凸塊來直接連接至該等快取接觸墊。在又另一形式中，該第一半導體晶粒具有一比該第二半導體晶粒更大的表面面積。在又另一形式中，該第一半導體晶粒沿該第一半導體晶粒之一周邊具有外部接觸墊，用於自該第一半導體晶粒進行外部連接。在又另一形式中，一插入物係在該等主表面之間，用於將該等處理器接觸墊連接至該等快取接觸墊。在又另一形式中，該插入物具有用於將功率載送至由該第一半導體晶粒與該第二半導體晶粒組成之一群組之至少一者的跡線。在又另一形式中，該插入物延伸超出該第一半導體晶粒與該第二半導體晶粒之一外邊界外。在又另一形式中，該等處理器單元具有一第一面積，而且該等快取單元具有一第二面積，其中該第一區域與該第二區域係實質上相同。在又另一形式中，該等處理器單元與該等快取單元之外邊界係毗連的。在又另一形式中，該等處理單元之每一者具有與其他處理單元相同的形狀與大小。在又另一形式中，該處理單元陣列具有一第一幾何形狀且該快取單元陣列具有一第二幾何形狀，其係該第一幾何形狀之一鏡像。
在又另一形式中，提供一種製造一處理器/快取裝配件之方法。形成一處理器晶粒，其具有採取一第一配置的一處理器單元陣列並具有採取一第二配置的一第一複數個接觸墊。形成一快取晶粒，其具有採取一第三配置的一快取單元陣列並具有採取一第四配置的一第二複數個接觸墊。該第三配置係該第一配置之一鏡像，而該第四配置係該第二配置之一鏡像。該第一晶粒係接觸至該第二晶粒。在一形式中，形成該處理器晶粒係使用具有複數個處理器組之接觸墊的第一複數個接觸墊來加以實施，其中每一處理器組係由該等處理器單元之一者所獨有並具有用於載送一位址的一第一接觸墊子集。形成該快取晶粒係藉由具有複數個快取組之接觸墊的一第二複數個接觸墊來加以實施，其中每一快取組係由該等快取單元之一者所獨有並具有用於載送一位址的一第二接觸墊子集。在又另一形式中，將該第一晶粒接觸至該第二晶粒引起該等處理器單元之每一者與該等快取單元之一獨特者毗連。在又另一形式中，該接觸透過複數個焊料凸塊將該第一複數個接點直接連接至該第二複數個接點。在又另一形式中，該接觸係藉由提供一插入物並將該第一及第二晶粒連接至該插入物來加以實施。
在又另一形式中，提供一種處理器/快取裝配件，其具有一處理器晶粒，該處理器晶粒具有以一處理器單元陣列配置的第一、第二、第三及第四處理器單元。第一、第二、第三及第四組處理器接觸墊係在該處理器晶粒之一第一主表面上，其中該等第一、第二、第三及第四組處理器接觸墊係用於分別自該第一、第二、第三及第四處理器單元來載送位址。一快取晶粒具有以一快取單元陣列配置的第一、第二、第三及第四快取單元。第一、第二、第三及第四組快取接觸墊係在該快取晶粒之一第一主表面上，其中該等第一、第二、第三及第四組快取接觸墊係用於分別自該第一、第二、第三及第四處理器單元來接收位址，分別用於該第一、第二、第三及第四快取單元之使用。在又另一形式中，第五、第六、第七及第八組處理器接觸墊係在該處理器晶粒之該第一主表面上，其中該等第五、第六、第七及第八組處理器接觸墊係用於分別往返於該等第一、第二、第三及第四處理器單元來載送資料。第五、第六、第七及第八組快取接觸墊係在該快取晶粒之該第一主表面上，其中該等第五、第六、第七及第八組快取接觸墊係用於分別往返於該等第一、第二、第三及第四快取單元來載送資料。在又另一形式中，該等第一、第二、第三及第四快取單元係專用於分別供該等第一、第二、第三及第四處理器單元使用的快取。
因為實施本發明之設備大部分由熟習此項技術者已知之電子組件及電路構成，故為了瞭解並理解本發明之基本概念而且為了不模糊或偏離本發明之教示，將不在比如以上所解說視為必要者的任何更大程度上解釋電路細節。
而且，若有的話，在本說明書及在申請專利範圍中術語"前面"、"後面"、"頂部"、"底部"、"之上"、"底下"等用於說明性目的而不一定用於說明永久相對位置。應瞭解，如此使用的術語在適當情形下可互換使得本文中說明的本發明之具體實施例(例如)能夠以除本文中所解說或另外說明外的方位來操作。
適當時可使用各種不同資訊處理系統來實施以上具體實施例之一些。例如，實施該等揭示結構的一些系統可將該處理晶粒放置於兩個記憶體晶粒之間，其中單獨記憶體晶粒在該處理晶粒之頂部及下面。隨著多核心系統激增，可在一單一晶粒上實施任一數目的處理單元。類似地，一單一處理單元可具有處理單元之多個子單元。當然，為討論之目的已簡化架構之說明，且其僅係依據本發明可使用的許多不同類型適當架構之一者。熟習此項技術者將認識到邏輯區塊之間的邊界僅係解說性的且替代具體實施例可合併邏輯區塊或電路元件或在各種邏輯區塊或電路元件上強加功能性之一替代分解。
因而，應瞭解，本文中所描述的該等架構僅係範例性的，且實際上可實施獲得相同功能性之許多其他架構。在一抽象、但仍明確意義上，實現相同功能性之組件的任一配置均有效"相關聯"以使得實現所需的功能性。因此，可將本文中組合以實現一特定功能性的任何兩組件均可視為彼此"相關聯"使得實現所需功能性，而不管架構或中間組件如何。同樣地，還可將如此相關聯之任兩個組件視為彼此"可操作地連接"或"可操作地耦合"用以實現所需功能性。
此外，熟習此項技術者應認識到以上說明操作之功能性之間的邊界僅係解說性的。可將多個操作之功能性組合成一單一操作及/或可將一單一操作之功能性分佈於額外操作中。而且，替代性具體實施例可能包括一特定操作之多個執行體，且可在各種其他具體實施例中變更操作順序。
在一具體實施例中，本文中所說明的多處理器/記憶體快取系統係電腦系統，諸如一個人電腦系統。其他具體實施例可包括不同類型的電腦系統。電腦系統係資訊處置系統，其可經設計以向一或多個使用者賦予獨立計算能力。電腦系統可訴諸於許多形式，包括(但不限於)主機電腦、小型電腦、伺服器、工作站、個人電腦、文字編譯器、個人數位助理、電子遊戲、自動及其他嵌入式系統、行動電話及各種其他無線裝置。一典型電腦系統包括至少一處理單元、相關聯記憶體及許多輸入/輸出(I/O)裝置。
一電腦系統依據一程式來處理資訊而且經由I/O裝置來產生所得輸出資訊。一程式係一指令清單，諸如一特定應用程式及/或一作業系統。一電腦程式一般內部儲存於電腦可讀取儲存媒體上或經由一電腦可讀取傳輸媒體來發送至電腦系統。一電腦程序一般包括一程式之一執行(運行)程式或部分、目前程式值及狀態資訊以及供操作系統用以管理該程序之執行的資源。一母處理可生出其他子處理以幫助實行該母處理之總功能性。因為該母處理明確生出該等子處理以實行該母處理之總功能性的一部分，故子處理(以及孫程序等)所實行的該等功能可有時說明為由該母處理來實行。
儘管本文中參考特定具體實施例來說明本發明，但可進行各種修改及改變而不脫離以下申請專利範圍中所提出的本發明之範疇。例如，可使用除導電凸塊外的其他形式導電接點。在一形式中，可使用在該半導體晶粒及該插入物兩者上的導電墊。因此，該說明書及圖式應視為解說性而非限制性，且所有此類的修改皆意在包括於本發明之範疇內。於本文中關於特定具體實施例所說明的任何好處、優點或問題解決方式並不意在解釋為任一或所有申請項之關鍵、必要或本質特徵或元件。
本文中使用的術語"耦合"並不意在限於一直接耦合或一機械耦合。
另外，本文所使用的術語"一"或"一個"係定義為一個或一個以上。並且，在申請專利範圍中諸如"至少一"及"一或多個"之介紹性短語的使用不應解釋為暗示著藉由不定冠詞"一"或"一個"介紹另一請求項元件將含有此類介紹請求項元件之任一特定請求項限於僅含有一此類元件之發明，即使相同請求項包括該介紹性短語"一或多個"或"至少一"以及諸如"一"或"一個"之不定冠詞。此點亦適用於定冠詞的用法。
除非另外聲明，否則諸如"第一"及"第二"之術語係用於任意區別此類術語所說明的該等元件。因而，此等術語不一定意在指示此類元件之時間或其他優先次序。
9．．．處理器晶粒
10．．．處理器晶粒
11至35．．．處理單元
38．．．外部連接區域
40．．．外部接觸墊
42．．．外部接觸墊
44．．．外部接觸墊
45．．．快取晶粒
46至70．．．快取單元
72．．．處理器/快取裝配件
73、74、75、76、77．．．處理器/快取
80．．．資料匯流排
82．．．位址匯流排
84．．．控制匯流排
86．．．狀態匯流排
88．．．多處理器/快取裝配件
90．．．插入物
92、94．．．外部接點
96、97．．．導電導孔
98至101．．．導電凸塊
102、104．．．接觸墊/快取組
103、105．．．接觸墊/處理器組
114．．．資料跡線
C1、C2、C3、C4、C5(56、57、58、59、60)．．．快取單元
P1、P2、P3、P4、P5(21、22、23、24、25)．．．處理單元
本發明係藉由範例方式來進行解說且不受該等附圖限制，其中相同參考指示相似元件。圖中的元件係為了解說之簡化及清楚之目的而解說且不一定按比例繪製。
圖1以示意形式解說依據一第一具體實施例具有複數個單獨處理單元之一第一半導體晶粒；
圖2以示意形式解說依據一第二具體實施例具有複數個單獨處理單元之該第一半導體晶粒；
圖3以示意形式解說具有複數個半導體快取單元的一第二半導體晶粒，每一半導體快取單元與該第一半導體晶粒之一特定處理單元相關；
圖4以斷面形式解說當經由相關聯功能連接來接合圖3之第二半導體晶粒時圖2之第一半導體晶粒的實體屬性；
圖5以斷面形式解說當經由一插入物及相關聯功能連接來接合圖3之該第二半導體晶粒時圖1之第一半導體晶粒的實體屬性；
圖6以斷面形式解說當將該第一半導體晶粒之一部分連接至該第二半導體晶粒時圖5之插入物的實體屬性。
10．．．處理器晶粒
21至25．．．處理單元
38．．．外部連接區域
40．．．外部接觸墊
45．．．快取晶粒
56至60．．．快取單元
72．．．處理器/快取裝配件
73、74、75、76、77．．．處理器/快取
80．．．資料匯流排
82．．．位址匯流排
84．．．控制匯流排
86．．．狀態匯流排
C1、C2、C3、C4、C5(56、57、58、59、60)．．．快取單元
P1、P2、P3、P4、P5(21、22、23、24、25)．．．處理單元

Claims (10)

  1. 一種處理器/快取裝配件，其包含：一第一半導體晶粒，其具有一處理單元陣列，其中：該處理單元陣列之每一處理單元具有一組處理器接觸墊；該組處理器接觸墊係在該第一半導體晶粒之一表面上的導電墊；每一組處理器接觸墊係獨特於該處理單元陣列之所有其他處理單元之該組處理器接觸墊；以及每一組處理器接觸墊包括用於位址信號之一第一處理器接觸墊子集，及用於資料信號之一第二處理器接觸墊子集；以及一第二半導體晶粒，其具有一快取單元陣列，其中：該快取單元陣列之每一快取單元具有一組快取接觸墊；該組快取接觸墊係在該第二半導體晶粒外之一表面上的導電墊；每一組快取接觸墊係獨特於該快取單元陣列之所有其他快取單元之該組快取接觸墊；每一組外部接觸墊包括用於位址信號之一第一快取接觸墊子集，及用於資料信號之一第二快取接觸墊子集；每一快取單元之該第一快取接觸墊子集係連接至該等處理單元之一獨特者之該第一處理器接觸墊子集； 以及每一快取單元之該第二快取接觸墊子集係連接至其第一快取接觸墊子集所連接之該處理單元之該第二處理器接觸墊子集。
  2. 如請求項1之處理器/快取裝配件，其中：該第一半導體晶粒具有一主表面；該等處理器接觸墊係在該第一半導體晶粒之該主表面上；該第二半導體晶粒具有一主表面；該等快取接觸墊係在該第二半導體晶粒之該主表面上；以及該第一半導體晶粒之該主表面面向該第二半導體晶粒之該主表面。
  3. 如請求項2之處理器/快取裝配件，其中該等處理器接觸墊係透過導電凸塊直接連接至該等快取接觸墊。
  4. 如請求項3之處理器/快取裝配件，其中該第一半導體晶粒之進一步特徵為具有比該第二半導體晶粒更大之一表面面積。
  5. 如請求項4之處理器/快取裝配件，其中該第一半導體晶粒沿該第一半導體晶粒之一周邊具有外部接觸墊，用於自該第一半導體晶粒進行外部連接。
  6. 如請求項2之處理器/快取裝配件，進一步包含在該第一半導體晶粒與該第二半導體晶粒之每一主表面之間的一插入物，用於將該等處理器接觸墊連接至該等快取接觸 墊。
  7. 如請求項6之處理器/快取裝配件，其中該插入物具有用於將功率載送至由該第一半導體晶粒與該第二半導體晶粒組成之一群組之至少一者的跡線。
  8. 如請求項7之處理器/快取裝配件，其中該插入物延伸超出該第一半導體晶粒與該第二半導體晶粒之一外邊界外。
  9. 一種處理器/快取裝配件，其包含：一處理器晶粒，其具有以一處理器單元陣列配置的第一、第二、第三及第四處理器單元；在該處理器晶粒之一第一主表面上的第一、第二、第三及第四組處理器接觸墊，其中該等第一、第二、第三及第四組處理器接觸墊係用於分別自該等第一、第二、第三及第四處理器單元來載送位址；一快取晶粒，其具有以一快取單元陣列配置的第一、第二、第三及第四快取單元；在該快取晶粒之一第一主表面上的第一、第二、第三及第四組快取接觸墊，其中該等第一、第二、第三及第四組快取接觸墊係用於分別自該等第一、第二、第三及第四處理器單元接收位址，分別用於該等第一、第二、第三及第四快取單元之使用。
  10. 如請求項9之處理器/快取裝配件，進一步包含：在該處理器晶粒之該第一主表面上的第五、第六、第七及第八組處理器接觸墊，其中該等第五、第六、第七 及第八組處理器接觸墊係用於分別往返於該等第一、第二、第三及第四處理器單元來載送資料；以及在該快取晶粒之該第一主表面上的第五、第六、第七及第八組快取接觸墊，其中該等第五、第六、第七及第八組快取接觸墊係用於分別往返於該等第一、第二、第三及第四快取單元來載送資料。
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