JP2009212503A - Ｓｏｉ基板の作製方法 - Google Patents

Ｓｏｉ基板の作製方法 Download PDF

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Publication number
JP2009212503A
JP2009212503A JP2009022434A JP2009022434A JP2009212503A JP 2009212503 A JP2009212503 A JP 2009212503A JP 2009022434 A JP2009022434 A JP 2009022434A JP 2009022434 A JP2009022434 A JP 2009022434A JP 2009212503 A JP2009212503 A JP 2009212503A
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JP
Japan
Prior art keywords
single crystal
semiconductor substrate
crystal semiconductor
insulating film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2009022434A
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English (en)
Japanese (ja)
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JP2009212503A5 (enExample
Inventor
Hideto Onuma
英人 大沼
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2009022434A priority Critical patent/JP2009212503A/ja
Publication of JP2009212503A publication Critical patent/JP2009212503A/ja
Publication of JP2009212503A5 publication Critical patent/JP2009212503A5/ja
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
JP2009022434A 2008-02-04 2009-02-03 Ｓｏｉ基板の作製方法 Withdrawn JP2009212503A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009022434A JP2009212503A (ja) 2008-02-04 2009-02-03 Ｓｏｉ基板の作製方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008024608 2008-02-04
JP2009022434A JP2009212503A (ja) 2008-02-04 2009-02-03 Ｓｏｉ基板の作製方法

Publications (2)

Publication Number Publication Date
JP2009212503A true JP2009212503A (ja) 2009-09-17
JP2009212503A5 JP2009212503A5 (enExample) 2012-01-19

Family

ID=40932097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009022434A Withdrawn JP2009212503A (ja) 2008-02-04 2009-02-03 Ｓｏｉ基板の作製方法

Country Status (3)

Country Link
US (1) US7858495B2 (enExample)
JP (1) JP2009212503A (enExample)
KR (1) KR101596454B1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011146701A (ja) * 2009-12-17 2011-07-28 Infineon Technologies Austria Ag 酸化物層を有する半導体部品
JP2014135496A (ja) * 2010-04-23 2014-07-24 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法

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JP2009141093A (ja) * 2007-12-06 2009-06-25 Toshiba Corp 発光素子及び発光素子の製造方法
JP5654206B2 (ja) * 2008-03-26 2015-01-14 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法及び該ｓｏｉ基板を用いた半導体装置
JP2009260315A (ja) * 2008-03-26 2009-11-05 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法及び半導体装置の作製方法
JP2011077504A (ja) * 2009-09-02 2011-04-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
SG173283A1 (en) * 2010-01-26 2011-08-29 Semiconductor Energy Lab Method for manufacturing soi substrate
EP2615645A1 (en) * 2012-01-10 2013-07-17 Innovation & Infinity Global Corp. Composite poly-silicon substrate and solar cell having the same
KR102031174B1 (ko) * 2012-11-16 2019-10-11 삼성전자주식회사 반도체 소자, 반도체 소자의 제조 방법 및 기판 가공 장치
US9589853B2 (en) 2014-02-28 2017-03-07 Lam Research Corporation Method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber
CN106252458B (zh) * 2015-06-10 2017-12-12 Lg电子株式会社 制造太阳能电池的方法
US9960275B1 (en) * 2016-10-28 2018-05-01 Applied Materials, Inc. Method of fabricating air-gap spacer for N7/N5 finFET and beyond
CN117038572A (zh) * 2017-07-14 2023-11-10 太阳能爱迪生半导体有限公司 绝缘体上半导体结构的制造方法
TWI796599B (zh) * 2019-09-30 2023-03-21 台灣積體電路製造股份有限公司 絕緣層上半導體（soi）基底、形成絕緣層上半導體基底的方法以及積體電路
US11289330B2 (en) 2019-09-30 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator (SOI) substrate and method for forming

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
JPH09275216A (ja) * 1996-02-09 1997-10-21 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2000077287A (ja) * 1998-08-26 2000-03-14 Nissin Electric Co Ltd 結晶薄膜基板の製造方法
JP2001203340A (ja) * 2000-01-21 2001-07-27 Nissin Electric Co Ltd シリコン系結晶薄膜の形成方法
WO2005022610A1 (ja) * 2003-09-01 2005-03-10 Sumco Corporation 貼り合わせウェーハの製造方法
WO2005055293A1 (ja) * 2003-12-02 2005-06-16 Bondtech Inc. 接合方法及びこの方法により作成されるデバイス並びに表面活性化装置及びこの装置を備えた接合装置
WO2007006803A1 (fr) * 2005-07-13 2007-01-18 S.O.I.Tec Silicon On Insulator Technologies Procede de diminution de la rugosite d'une couche epaisse d'isolant
JP2007194345A (ja) * 2006-01-18 2007-08-02 Canon Inc はり合わせ基板の製造方法、及びはり合わせ基板の製造装置
JP2008535230A (ja) * 2005-04-22 2008-08-28 エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ 半導体材料から選択された材料で作られた２つのウェハを貼り合わせる方法

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FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP2000012864A (ja) * 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US6566233B2 (en) * 1999-12-24 2003-05-20 Shin-Etsu Handotai Co., Ltd. Method for manufacturing bonded wafer
US7713838B2 (en) * 2003-09-08 2010-05-11 Sumco Corporation SOI wafer and its manufacturing method
US8138061B2 (en) * 2005-01-07 2012-03-20 International Business Machines Corporation Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide
US7745309B2 (en) * 2006-08-09 2010-06-29 Applied Materials, Inc. Methods for surface activation by plasma immersion ion implantation process utilized in silicon-on-insulator structure
CN101281912B (zh) * 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
KR101447048B1 (ko) * 2007-04-20 2014-10-06 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｓｏｉ 기판 및 반도체장치의 제조방법
KR101436116B1 (ko) * 2007-04-27 2014-09-01 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｓｏｉ 기판 및 그 제조 방법, 및 반도체 장치

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
JPH09275216A (ja) * 1996-02-09 1997-10-21 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2000077287A (ja) * 1998-08-26 2000-03-14 Nissin Electric Co Ltd 結晶薄膜基板の製造方法
JP2001203340A (ja) * 2000-01-21 2001-07-27 Nissin Electric Co Ltd シリコン系結晶薄膜の形成方法
WO2005022610A1 (ja) * 2003-09-01 2005-03-10 Sumco Corporation 貼り合わせウェーハの製造方法
WO2005055293A1 (ja) * 2003-12-02 2005-06-16 Bondtech Inc. 接合方法及びこの方法により作成されるデバイス並びに表面活性化装置及びこの装置を備えた接合装置
JP2008535230A (ja) * 2005-04-22 2008-08-28 エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ 半導体材料から選択された材料で作られた２つのウェハを貼り合わせる方法
WO2007006803A1 (fr) * 2005-07-13 2007-01-18 S.O.I.Tec Silicon On Insulator Technologies Procede de diminution de la rugosite d'une couche epaisse d'isolant
JP2007194345A (ja) * 2006-01-18 2007-08-02 Canon Inc はり合わせ基板の製造方法、及びはり合わせ基板の製造装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011146701A (ja) * 2009-12-17 2011-07-28 Infineon Technologies Austria Ag 酸化物層を有する半導体部品
JP2014135496A (ja) * 2010-04-23 2014-07-24 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US9099499B2 (en) 2010-04-23 2015-08-04 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US9245983B2 (en) 2010-04-23 2016-01-26 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
US7858495B2 (en) 2010-12-28
KR101596454B1 (ko) 2016-02-22
KR20090085533A (ko) 2009-08-07
US20090197391A1 (en) 2009-08-06

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