JP2009200471A5 - - Google Patents
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- JP2009200471A5 JP2009200471A5 JP2008319711A JP2008319711A JP2009200471A5 JP 2009200471 A5 JP2009200471 A5 JP 2009200471A5 JP 2008319711 A JP2008319711 A JP 2008319711A JP 2008319711 A JP2008319711 A JP 2008319711A JP 2009200471 A5 JP2009200471 A5 JP 2009200471A5
- Authority
- JP
- Japan
- Prior art keywords
- fin
- layer
- trench
- semiconductor material
- active region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 claims description 290
- 239000000463 material Substances 0.000 claims description 145
- 238000000034 method Methods 0.000 claims description 77
- 239000013078 crystal Substances 0.000 claims description 69
- 239000000758 substrate Substances 0.000 claims description 67
- 230000008569 process Effects 0.000 claims description 46
- 238000004519 manufacturing process Methods 0.000 claims description 28
- 239000003989 dielectric material Substances 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 26
- 238000005530 etching Methods 0.000 description 14
- 230000008901 benefit Effects 0.000 description 11
- 238000001020 plasma etching Methods 0.000 description 9
- 239000012212 insulator Substances 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910003811 SiGeC Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US1513507P | 2007-12-19 | 2007-12-19 | |
| US61/015,135 | 2007-12-19 | ||
| EP08153677A EP2073267A1 (en) | 2007-12-19 | 2008-03-29 | Method of fabricating multi-gate semiconductor devices and devices obtained |
| EP08153677.3 | 2008-03-29 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009200471A JP2009200471A (ja) | 2009-09-03 |
| JP2009200471A5 true JP2009200471A5 (enExample) | 2012-01-26 |
| JP5464850B2 JP5464850B2 (ja) | 2014-04-09 |
Family
ID=39673249
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008319711A Active JP5464850B2 (ja) | 2007-12-19 | 2008-12-16 | 改良されたキャリア移動度を有するマルチゲート半導体デバイスの製造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US7842559B2 (enExample) |
| EP (1) | EP2073267A1 (enExample) |
| JP (1) | JP5464850B2 (enExample) |
Families Citing this family (73)
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| US20090057846A1 (en) * | 2007-08-30 | 2009-03-05 | Doyle Brian S | Method to fabricate adjacent silicon fins of differing heights |
| US8106459B2 (en) | 2008-05-06 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs having dielectric punch-through stoppers |
| US8048723B2 (en) * | 2008-12-05 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs having dielectric punch-through stoppers |
| US8263462B2 (en) | 2008-12-31 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dielectric punch-through stoppers for forming FinFETs having dual fin heights |
| US8293616B2 (en) | 2009-02-24 | 2012-10-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of fabrication of semiconductor devices with low capacitance |
| US8592918B2 (en) * | 2009-10-28 | 2013-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming inter-device STI regions and intra-device STI regions using different dielectric materials |
| DE102009046246B4 (de) * | 2009-10-30 | 2012-04-12 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Herstellverfahren und Halbleiterbauelement mit Verformungstechnologie in dreidimensionalen Transistoren auf der Grundlage global verformter Halbleiterbasisschichten |
| US8125007B2 (en) * | 2009-11-20 | 2012-02-28 | International Business Machines Corporation | Integrated circuit including FinFET RF switch angled relative to planar MOSFET and related design structure |
| CN102104069B (zh) * | 2009-12-16 | 2012-11-21 | 中国科学院微电子研究所 | 鳍式晶体管结构及其制作方法 |
| CN102117829B (zh) * | 2009-12-30 | 2012-11-21 | 中国科学院微电子研究所 | 鳍式晶体管结构及其制作方法 |
| US8344425B2 (en) * | 2009-12-30 | 2013-01-01 | Intel Corporation | Multi-gate III-V quantum well structures |
| US8575653B2 (en) * | 2010-09-24 | 2013-11-05 | Intel Corporation | Non-planar quantum well device having interfacial layer and method of forming same |
| US8524545B2 (en) | 2010-10-22 | 2013-09-03 | International Business Machines Corporation | Simultaneous formation of FinFET and MUGFET |
| US8524546B2 (en) | 2010-10-22 | 2013-09-03 | International Business Machines Corporation | Formation of multi-height MUGFET |
| US20120280354A1 (en) * | 2011-05-05 | 2012-11-08 | Synopsys, Inc. | Methods for fabricating high-density integrated circuit devices |
| US20140193963A1 (en) * | 2011-05-16 | 2014-07-10 | Varian Semiconductor Equipment Associates, Inc. | Techniques For Forming 3D Structures |
| US8716072B2 (en) | 2011-07-25 | 2014-05-06 | International Business Machines Corporation | Hybrid CMOS technology with nanowire devices and double gated planar devices |
| CN102903750B (zh) * | 2011-07-27 | 2015-11-25 | 中国科学院微电子研究所 | 一种半导体场效应晶体管结构及其制备方法 |
| US8420459B1 (en) | 2011-10-20 | 2013-04-16 | International Business Machines Corporation | Bulk fin-field effect transistors with well defined isolation |
| CN103107192B (zh) * | 2011-11-10 | 2016-05-18 | 中芯国际集成电路制造(北京)有限公司 | 半导体装置及其制造方法 |
| US9406518B2 (en) | 2011-11-18 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | (110) surface orientation for reducing fermi-level-pinning between high-K dielectric and group III-V compound semiconductor substrate |
| US20130175618A1 (en) * | 2012-01-05 | 2013-07-11 | International Business Machines Corporation | Finfet device |
| US8466012B1 (en) * | 2012-02-01 | 2013-06-18 | International Business Machines Corporation | Bulk FinFET and SOI FinFET hybrid technology |
| US8860148B2 (en) * | 2012-04-11 | 2014-10-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for FinFET integrated with capacitor |
| CN103377930B (zh) * | 2012-04-19 | 2015-11-25 | 中国科学院微电子研究所 | 半导体结构及其制造方法 |
| CN103378005B (zh) * | 2012-04-23 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | 多栅极场效应晶体管鳍状结构的制造方法 |
| CN103515231B (zh) * | 2012-06-20 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | FinFET制造方法 |
| US9425212B2 (en) | 2012-06-29 | 2016-08-23 | Intel Corporation | Isolated and bulk semiconductor devices formed on a same bulk substrate |
| US8673718B2 (en) * | 2012-07-09 | 2014-03-18 | Globalfoundries Inc. | Methods of forming FinFET devices with alternative channel materials |
| US8802565B2 (en) | 2012-09-10 | 2014-08-12 | International Business Machines Corporation | Semiconductor plural gate lengths |
| US9437475B2 (en) | 2012-11-08 | 2016-09-06 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for fabricating microelectronic devices with isolation trenches partially formed under active regions |
| US8946063B2 (en) | 2012-11-30 | 2015-02-03 | International Business Machines Corporation | Semiconductor device having SSOI substrate with relaxed tensile stress |
| US8828818B1 (en) | 2013-03-13 | 2014-09-09 | Samsung Electronics Co., Ltd. | Methods of fabricating integrated circuit device with fin transistors having different threshold voltages |
| US9236444B2 (en) * | 2013-05-03 | 2016-01-12 | Samsung Electronics Co., Ltd. | Methods of fabricating quantum well field effect transistors having multiple delta doped layers |
| US9331201B2 (en) | 2013-05-31 | 2016-05-03 | Globalfoundries Inc. | Multi-height FinFETs with coplanar topography background |
| US10170315B2 (en) | 2013-07-17 | 2019-01-01 | Globalfoundries Inc. | Semiconductor device having local buried oxide |
| US9023697B2 (en) | 2013-08-08 | 2015-05-05 | International Business Machines Corporation | 3D transistor channel mobility enhancement |
| EP2849219A1 (en) * | 2013-09-11 | 2015-03-18 | IMEC vzw | Method for manufacturing transistors and associated substrate |
| US9093275B2 (en) * | 2013-10-22 | 2015-07-28 | International Business Machines Corporation | Multi-height multi-composition semiconductor fins |
| US9252272B2 (en) | 2013-11-18 | 2016-02-02 | Globalfoundries Inc. | FinFET semiconductor device having local buried oxide |
| US9412818B2 (en) * | 2013-12-09 | 2016-08-09 | Qualcomm Incorporated | System and method of manufacturing a fin field-effect transistor having multiple fin heights |
| US9337258B2 (en) | 2013-12-20 | 2016-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a FinFET device |
| US9373706B2 (en) | 2014-01-24 | 2016-06-21 | Samsung Electronics Co., Ltd. | Methods of forming semiconductor devices, including forming a semiconductor material on a fin, and related semiconductor devices |
| US9190328B2 (en) | 2014-01-30 | 2015-11-17 | International Business Machines Corporation | Formation of fins having different heights in fin field effect transistors |
| US9123585B1 (en) | 2014-02-11 | 2015-09-01 | International Business Machines Corporation | Method to form group III-V and Si/Ge FINFET on insulator |
| US9129863B2 (en) * | 2014-02-11 | 2015-09-08 | International Business Machines Corporation | Method to form dual channel group III-V and Si/Ge FINFET CMOS |
| CN105097536A (zh) * | 2014-05-12 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
| US9190329B1 (en) * | 2014-05-20 | 2015-11-17 | International Business Machines Corporation | Complex circuits utilizing fin structures |
| US9196479B1 (en) | 2014-07-03 | 2015-11-24 | International Business Machines Corporation | Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin structures |
| US9362182B2 (en) | 2014-11-06 | 2016-06-07 | International Business Machines Corporation | Forming strained fins of different material on a substrate |
| US9455274B2 (en) * | 2015-01-30 | 2016-09-27 | International Business Machines Corporation | Replacement fin process in SSOI wafer |
| US9865710B2 (en) | 2015-03-31 | 2018-01-09 | Stmicroelectronics, Inc. | FinFET having a non-uniform fin |
| EP3314665A4 (en) | 2015-06-26 | 2019-02-20 | INTEL Corporation | CAVITATE-BASED INTEGRATION OF HETEROEPITACTIC N-TYPE TRANSISTORS WITH P-TYPE TRANSISTORS |
| US10985278B2 (en) * | 2015-07-21 | 2021-04-20 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| US9548386B1 (en) | 2015-08-31 | 2017-01-17 | International Business Machines Corporation | Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices |
| US9589965B1 (en) * | 2016-01-22 | 2017-03-07 | Globalfoundries Inc. | Controlling epitaxial growth over eDRAM deep trench and eDRAM so formed |
| CN107316814B (zh) * | 2016-04-26 | 2021-11-23 | 联华电子股份有限公司 | 半导体元件的制造方法 |
| US10290654B2 (en) | 2016-05-20 | 2019-05-14 | Globalfoundries Inc. | Circuit structures with vertically spaced transistors and fabrication methods |
| US10147802B2 (en) * | 2016-05-20 | 2018-12-04 | Globalfoundries Inc. | FINFET circuit structures with vertically spaced transistors and fabrication methods |
| US9882000B2 (en) | 2016-05-24 | 2018-01-30 | Northrop Grumman Systems Corporation | Wrap around gate field effect transistor (WAGFET) |
| US9768075B1 (en) | 2016-06-20 | 2017-09-19 | International Business Machines Corporation | Method and structure to enable dual channel fin critical dimension control |
| US9847418B1 (en) * | 2016-07-26 | 2017-12-19 | Globalfoundries Inc. | Methods of forming fin cut regions by oxidizing fin portions |
| US10535680B2 (en) * | 2017-06-29 | 2020-01-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit structure and method with hybrid orientation for FinFET |
| DE102017127253B4 (de) | 2017-06-29 | 2024-02-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrierte schaltkreisstruktur und verfahren mit hybridorientierung für finfet |
| US11251270B2 (en) * | 2017-08-02 | 2022-02-15 | Faquir Chand Jain | Quantum dot channel (QDC) quantum dot gate transistors, memories and other devices |
| US10269803B2 (en) * | 2017-08-31 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid scheme for improved performance for P-type and N-type FinFETs |
| KR102592872B1 (ko) | 2018-04-10 | 2023-10-20 | 삼성전자주식회사 | 반도체 장치 |
| US10930569B2 (en) * | 2018-07-31 | 2021-02-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual crystal orientation for semiconductor devices |
| US10679992B1 (en) * | 2018-11-16 | 2020-06-09 | International Business Machines Corporation | Integrated device with vertical field-effect transistors and hybrid channels |
| WO2022217541A1 (zh) * | 2021-04-15 | 2022-10-20 | 苏州晶湛半导体有限公司 | 半导体结构及其制备方法 |
| US12336246B2 (en) | 2021-05-06 | 2025-06-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures with a hybrid substrate |
| CN115995480B (zh) * | 2021-10-18 | 2025-09-02 | 长鑫存储技术有限公司 | 半导体器件及其制备方法与应用 |
| WO2023157627A1 (ja) * | 2022-02-18 | 2023-08-24 | ソニーセミコンダクタソリューションズ株式会社 | 比較器、光検出素子および電子機器 |
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| JP2002118255A (ja) * | 2000-07-31 | 2002-04-19 | Toshiba Corp | 半導体装置およびその製造方法 |
| JP2002289871A (ja) * | 2001-03-28 | 2002-10-04 | Toshiba Corp | 半導体装置及びその製造方法 |
| KR100487566B1 (ko) * | 2003-07-23 | 2005-05-03 | 삼성전자주식회사 | 핀 전계 효과 트랜지스터 및 그 형성 방법 |
| US6835618B1 (en) * | 2003-08-05 | 2004-12-28 | Advanced Micro Devices, Inc. | Epitaxially grown fin for FinFET |
| JPWO2005020325A1 (ja) * | 2003-08-26 | 2007-11-01 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| US6995456B2 (en) * | 2004-03-12 | 2006-02-07 | International Business Machines Corporation | High-performance CMOS SOI devices on hybrid crystal-oriented substrates |
| US6998684B2 (en) * | 2004-03-31 | 2006-02-14 | International Business Machines Corporation | High mobility plane CMOS SOI |
| US7087965B2 (en) * | 2004-04-22 | 2006-08-08 | International Business Machines Corporation | Strained silicon CMOS on hybrid crystal orientations |
| US7291886B2 (en) | 2004-06-21 | 2007-11-06 | International Business Machines Corporation | Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs |
| US7538351B2 (en) | 2005-03-23 | 2009-05-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming an SOI structure with improved carrier mobility and ESD protection |
| US7439108B2 (en) * | 2005-06-16 | 2008-10-21 | International Business Machines Corporation | Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same |
| US7737532B2 (en) * | 2005-09-06 | 2010-06-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid Schottky source-drain CMOS for high mobility and low barrier |
| US7547947B2 (en) * | 2005-11-15 | 2009-06-16 | International Business Machines Corporation | SRAM cell |
| KR100653536B1 (ko) | 2005-12-29 | 2006-12-05 | 동부일렉트로닉스 주식회사 | 반도체 소자의 핀 전계효과 트랜지스터 제조방법 |
| US7456055B2 (en) | 2006-03-15 | 2008-11-25 | Freescale Semiconductor, Inc. | Process for forming an electronic device including semiconductor fins |
| US7365401B2 (en) * | 2006-03-28 | 2008-04-29 | International Business Machines Corporation | Dual-plane complementary metal oxide semiconductor |
| US7435639B2 (en) * | 2006-05-31 | 2008-10-14 | Freescale Semiconductor, Inc. | Dual surface SOI by lateral epitaxial overgrowth |
| KR100741468B1 (ko) * | 2006-07-10 | 2007-07-20 | 삼성전자주식회사 | 반도체 장치 및 그 형성 방법 |
| US7803670B2 (en) * | 2006-07-20 | 2010-09-28 | Freescale Semiconductor, Inc. | Twisted dual-substrate orientation (DSO) substrates |
| US7595232B2 (en) * | 2006-09-07 | 2009-09-29 | International Business Machines Corporation | CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors |
| JP2008227026A (ja) * | 2007-03-12 | 2008-09-25 | Toshiba Corp | 半導体装置の製造方法 |
-
2008
- 2008-03-29 EP EP08153677A patent/EP2073267A1/en not_active Withdrawn
- 2008-12-16 JP JP2008319711A patent/JP5464850B2/ja active Active
- 2008-12-19 US US12/340,302 patent/US7842559B2/en active Active
-
2010
- 2010-11-19 US US12/950,977 patent/US8445963B2/en active Active
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