JP2009182272A - 素子搭載用基板およびその製造方法、半導体モジュールおよびその製造方法、ならびに携帯機器 - Google Patents

素子搭載用基板およびその製造方法、半導体モジュールおよびその製造方法、ならびに携帯機器 Download PDF

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Publication number
JP2009182272A
JP2009182272A JP2008022011A JP2008022011A JP2009182272A JP 2009182272 A JP2009182272 A JP 2009182272A JP 2008022011 A JP2008022011 A JP 2008022011A JP 2008022011 A JP2008022011 A JP 2008022011A JP 2009182272 A JP2009182272 A JP 2009182272A
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JP
Japan
Prior art keywords
electrode
protruding electrode
insulating resin
resin layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008022011A
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English (en)
Japanese (ja)
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JP2009182272A5 (https=
Inventor
Mayumi Nakazato
真弓 中里
Katsumi Ito
克実 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2008022011A priority Critical patent/JP2009182272A/ja
Priority to CNA2009101307726A priority patent/CN101510539A/zh
Priority to US12/363,983 priority patent/US8283568B2/en
Publication of JP2009182272A publication Critical patent/JP2009182272A/ja
Publication of JP2009182272A5 publication Critical patent/JP2009182272A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2008022011A 2008-01-31 2008-01-31 素子搭載用基板およびその製造方法、半導体モジュールおよびその製造方法、ならびに携帯機器 Pending JP2009182272A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008022011A JP2009182272A (ja) 2008-01-31 2008-01-31 素子搭載用基板およびその製造方法、半導体モジュールおよびその製造方法、ならびに携帯機器
CNA2009101307726A CN101510539A (zh) 2008-01-31 2009-02-01 元件搭载用基板、半导体组件及其制造方法及便携式设备
US12/363,983 US8283568B2 (en) 2008-01-31 2009-02-02 Device mounting board, and semiconductor module and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008022011A JP2009182272A (ja) 2008-01-31 2008-01-31 素子搭載用基板およびその製造方法、半導体モジュールおよびその製造方法、ならびに携帯機器

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011285081A Division JP5306443B2 (ja) 2011-12-27 2011-12-27 素子搭載用基板、素子搭載用基板の製造方法、半導体モジュールおよび半導体モジュールの製造方法

Publications (2)

Publication Number Publication Date
JP2009182272A true JP2009182272A (ja) 2009-08-13
JP2009182272A5 JP2009182272A5 (https=) 2011-03-10

Family

ID=40931490

Family Applications (1)

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JP2008022011A Pending JP2009182272A (ja) 2008-01-31 2008-01-31 素子搭載用基板およびその製造方法、半導体モジュールおよびその製造方法、ならびに携帯機器

Country Status (3)

Country Link
US (1) US8283568B2 (https=)
JP (1) JP2009182272A (https=)
CN (1) CN101510539A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011052744A1 (ja) * 2009-10-30 2011-05-05 三洋電機株式会社 素子搭載用基板およびその製造方法、半導体モジュール、ならびに携帯機器
JP2012064981A (ja) * 2011-12-27 2012-03-29 Sanyo Electric Co Ltd 素子搭載用基板、素子搭載用基板の製造方法、半導体モジュールおよび半導体モジュールの製造方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWM362572U (en) * 2009-04-13 2009-08-01 Phytrex Technology Corp Signal convertor
KR101088792B1 (ko) * 2009-11-30 2011-12-01 엘지이노텍 주식회사 인쇄회로기판 및 그 제조방법
JP5624699B1 (ja) * 2012-12-21 2014-11-12 パナソニック株式会社 電子部品パッケージおよびその製造方法
TWM470379U (zh) * 2013-09-05 2014-01-11 思鷺科技股份有限公司 陶瓷電路板及具有該陶瓷電路板的ｌｅｄ封裝模組
TWI550801B (zh) * 2013-11-13 2016-09-21 南茂科技股份有限公司 封裝結構及其製造方法
JP2016207893A (ja) * 2015-04-24 2016-12-08 イビデン株式会社 プリント配線板およびその製造方法
US12322719B2 (en) 2022-03-22 2025-06-03 Nxp Usa, Inc. Semiconductor device structure and method therefor
US20240014152A1 (en) * 2022-07-07 2024-01-11 Nxp B.V. Semiconductor device with under-bump metallization and method therefor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002141629A (ja) * 2000-11-01 2002-05-17 North:Kk 配線回路用部材とその製造方法と多層配線回路基板と半導体集積回路装置
JP2006310530A (ja) * 2005-04-28 2006-11-09 Sanyo Electric Co Ltd 回路装置およびその製造方法
WO2007063954A1 (ja) * 2005-11-30 2007-06-07 Sanyo Electric Co., Ltd. 回路装置および回路装置の製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3050807B2 (ja) * 1996-06-19 2000-06-12 イビデン株式会社 多層プリント配線板
AU6418998A (en) 1997-03-21 1998-10-20 Seiko Epson Corporation Semiconductor device, film carrier tape, and method for manufacturing them
KR100906931B1 (ko) * 1998-02-26 2009-07-10 이비덴 가부시키가이샤 필드 바이어 구조를 갖는 다층프린트 배선판
JP2004193297A (ja) 2002-12-11 2004-07-08 Dainippon Printing Co Ltd ウェハレベルパッケージおよびその製造方法
JP2007258207A (ja) 2006-03-20 2007-10-04 Three M Innovative Properties Co バンプ付きチップもしくはパッケージの実装方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002141629A (ja) * 2000-11-01 2002-05-17 North:Kk 配線回路用部材とその製造方法と多層配線回路基板と半導体集積回路装置
JP2006310530A (ja) * 2005-04-28 2006-11-09 Sanyo Electric Co Ltd 回路装置およびその製造方法
WO2007063954A1 (ja) * 2005-11-30 2007-06-07 Sanyo Electric Co., Ltd. 回路装置および回路装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011052744A1 (ja) * 2009-10-30 2011-05-05 三洋電機株式会社 素子搭載用基板およびその製造方法、半導体モジュール、ならびに携帯機器
JP2012064981A (ja) * 2011-12-27 2012-03-29 Sanyo Electric Co Ltd 素子搭載用基板、素子搭載用基板の製造方法、半導体モジュールおよび半導体モジュールの製造方法

Also Published As

Publication number Publication date
US20090196010A1 (en) 2009-08-06
US8283568B2 (en) 2012-10-09
CN101510539A (zh) 2009-08-19

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