JP2009170570A - 半導体装置の配線基板、半導体装置、電子装置およびマザーボード - Google Patents
半導体装置の配線基板、半導体装置、電子装置およびマザーボード Download PDFInfo
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- JP2009170570A JP2009170570A JP2008005275A JP2008005275A JP2009170570A JP 2009170570 A JP2009170570 A JP 2009170570A JP 2008005275 A JP2008005275 A JP 2008005275A JP 2008005275 A JP2008005275 A JP 2008005275A JP 2009170570 A JP2009170570 A JP 2009170570A
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
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Abstract
【解決手段】 半導体装置3の配線基板1は、基材13、基材13に設けられたソルダーレジスト21b、ランド9、配線25を有している。
ソルダーレジスト21bとランド9は接触しておらず、配線25の端部26は、ハンダボール11が設けられていない状態では、ランド9と互いに対向し、離間して設けられている。
そのため、ランド9と端部26の間には隙間31が形成され、ランド9は完全なNSMD構造を形成している。
ランド9上にハンダボール11を設けると、ハンダボール11が、端部26およびランド9を覆い、隙間31を埋めることにより、端部26とランド9が、電気的に接続される。
【選択図】 図3
Description
の番号を付し、説明を省略する。
3…………半導体装置
5…………半導体チップ
7…………封止部
9…………ランド
11………ハンダボール
13………基材
15………接続パッド
17………ワイヤ
19………電極パッド
21a……ソルダーレジスト
21b……ソルダーレジスト
23………接着剤
25………配線
26………端部
31………隙間
35………配線母基板
37………製品形成領域
39………枠部
41………ダイシングライン
43………位置決め孔
45………銅層
47………フォトレジスト
53………マウントツール
65………マザーボード
67a……ソルダーレジスト
69………ランド
71………基材
101……電子装置
Claims (21)
- 基材と、
前記基材上に設けられ、コンタクト部材を搭載するランドと、
前記基材上に設けられ、前記コンタクト部材と電気的に接続される配線と、
前記基材の表面を覆うように設けられ、かつ前記ランドとは接触しないように設けられたソルダーレジストと、
を有し、
前記配線は、前記ランドと離間して設けられていることを特徴とする半導体装置の配線基板。 - 前記配線は、前記ランドに隣接して設けられた端部を有し、
前記ソルダーレジストは、前記配線の前記端部と接触しないように設けられていることを特徴とする請求項1記載の半導体装置の配線基板。 - 前記端部は、前記ランドへ向けて拡幅した形状を有することを特徴とする請求項2記載の半導体装置の配線基板。
- 前記端部の外周のうち、前記ランドの外周と対向する部分は、前記ランドの外周に対応した形状を有することを特徴とする請求項2記載の半導体装置の配線基板。
- 前記端部の外周のうち、前記ランドと対向する部分は、平面形状が波形もしくはノコギリ形であることを特徴とする請求項2記載の半導体装置の配線基板。
- 前記配線は、前記端部が複数に分岐していることを特徴とする請求項2記載の半導体装置の配線基板。
- 前記ランドは、環状の平面形状を有する複数の環状ランドを有し、
複数の前記環状ランドは、同心円状に配置されていることを特徴とする請求項2記載の半導体装置の配線基板。 - 前記ランドは、切り欠き部を有し、
前記配線の少なくとも一部は、前記切り欠き部に設けられていることを特徴とする請求項2記載の半導体装置の配線基板。 - 前記基材は、
前記ランドと前記端部の間に貫通溝が設けられていることを特徴とする請求項2記載の半導体装置の配線基板。 - 前記ランドおよび前記端部を覆うように設けられたコンタクト部材をさらに有し、
前記コンタクト部材が、前記ランドおよび前記先端を覆うことにより、前記ランドと前記配線が電気的に接続されることを特徴とする請求項2記載の半導体装置の配線基板。 - 基材と、前記基材の一方の面に設けられた接続パッドと、前記基材の他の面に設けられ、前記接続パッドと電気的に接続された配線と、前記基材の他の面に設けられ、前記配線と離間して対向するように設けられたランドと、前記ランドと前記配線の一部が露出するように前記基材の他の面に設けられたソルダーレジストと、からなる配線基板と、
前記配線基板の一面に搭載され、前記接続パッドと電気的に接続された半導体チップと、少なくとも前記配線基板の一面と半導体チップの一部や全面を覆う封止体とを有する半導体装置において、
前記配線基板は、請求項1〜請求項10のいずれかに記載の半導体装置の配線基板であることを特徴とする半導体装置。 - 請求項1〜請求項10のいずれかに記載の半導体装置の配線基板の特徴を有するマザーボード。
- 請求項11記載の半導体装置を実装したマザーボードを備えていること、または請求項12記載のマザーボードを備えていることを特徴とする電子装置。
- 基材上に金属薄膜を形成した後に、前記金属薄膜を選択的にエッチングすることにより、
ランドと、
前記ランドと離間して設けられた配線と、
を配置する工程を有することを特徴とする半導体装置の配線基板の製造方法。 - 前記工程は、環状の平面形状を有し、同心円状に配置された複数個のランドを配置する工程を有することを特徴とする請求項14記載の半導体装置の半導体基板の製造方法。
- 前記工程は、環状の平面形状を有し、切り欠き部を有するランドを配置を配置する工程を有することを特徴とする請求項14記載の半導体装置の半導体基板の製造方法。
- 前記工程は、端部が複数に分岐した配線を配置する工程を有することを特徴とする請求項14記載の半導体装置の半導体基板の製造方法。
- 基材の表面を部分的に覆うようにソルダーレジストを設ける工程をさらに有し、
前記工程は、前記基材上に、ランドおよび前記配線の端部と接触しないように、前記ソルダーレジストを設ける工程であることを特徴とする請求項14〜請求項17のいずれかに記載の半導体装置の配線基板の製造方法。 - 前記ランドと前記配線の間を埋めて、両者を電気的に接続するようにコンタクト部材を設ける工程をさらに有することを特徴とする請求項18記載の半導体装置の配線基板の製造方法。
- 請求項1〜請求項10のいずれかに記載の半導体装置の配線基板上に半導体チップを搭載し、少なくとも前記半導体装置の配線基板の一面と半導体チップの一部や全面を封止体で覆い、前記ランド上にコンタクト部材を配置して前記ランドと前記半導体チップを電気的に接続し、半導体装置を製造する工程と、
前記半導体装置をマザーボード上に実装する工程と、
を有することを特徴とする電子装置の製造方法。 - 請求項1〜請求項10のいずれかに記載の半導体装置の配線基板の特徴を有するマザーボードの製造工程と、前記マザーボード上に半導体装置や電子部品を実装する工程と、を有することを特徴とする電子装置の製造方法。
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US8828802B1 (en) * | 2011-11-01 | 2014-09-09 | Amkor Technology, Inc. | Wafer level chip scale package and method of fabricating wafer level chip scale package |
JP6318638B2 (ja) * | 2014-01-17 | 2018-05-09 | 富士通株式会社 | プリント配線板および情報処理装置 |
US10665578B2 (en) | 2015-09-24 | 2020-05-26 | Apple Inc. | Display with embedded pixel driver chips |
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