JP2009152421A - 半導体素子、半導体装置、及びその製造方法 - Google Patents
半導体素子、半導体装置、及びその製造方法 Download PDFInfo
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Abstract
【解決手段】半導体素子1000は、内部回路142、内部回路と電気的に接続された電極144、及び内部回路を覆い、電極を露出して設けられた第1の絶縁層140が設けられた第1の半導体素子部分100と、電極と電気的に接続されるとともに第1の絶縁層上に形成され、第1のパッド211及び第2のパッド213を有する配線層210、及び第1のパッドと第2のパッドのいずれか一方を覆い、他方を露出させる第2の絶縁層220が設けられた第2の半導体素子部分200と、を有する。
【選択図】図1
Description
また、後者の場合、電極が形成された面の反対側の面がリードフレームに対向するようにリードフレームに搭載し、半導体素子の電極とリードフレームのリード端子とをワイヤボンディングを用いて電気的に接続させ、全体を樹脂封止するリードフレームパッケージや、電極が形成された面の反対側の面が搭載する対象の基板に対向するように搭載する対象の基板に搭載し、半導体素子の電極と基板の電極とをワイヤボンディングや配線層を形成することによって電気的に接続するCOBなどの実装形態が挙げられる。
このように多種多様の実装形態があるが、これらは半導体素子の機能、目的等に応じて適宜実装形態が選択され、また、搭載する対象の基板の電極の数や位置等に応じて適宜端子の位置等が設計される。
しかしながら、上述した従来の技術においては、半導体素子は、実装されるべき一つの形態に応じて設計がなされることが一般的であり、他の実装形態に対応するには再度設計しなおす必要があるなど、時間やコストを増大させる結果となっていた。
また、上述の特許文献1では、一つの実装形態についてパッド位置を変更するものであって、他の実装形態に応じるべくして行われているものではない。
第1の半導体素子部分100は、半導体層110、第1の層間絶縁膜120、第2の層間絶縁膜130、第3の層間絶縁膜140からなる。
配線層210は、第1の半導体素子部分100の第3の層間絶縁膜140上に形成される。配線層210は第3のコンタクト電極144上に形成される第1のパッド211と、第1のパッド211に接続される接続部212と、接続部212に接続される第2のパッド213とにより構成される。配線層210はアルミニウム、銅、またはそれらの合金から適宜選択され、本実施例では、アルミニウムと銅の合金を材料として用いており、その膜厚は800nmである。
図4に示す半導体素子1000の絶縁層220は、第2のパッド213を露出して形成されている。その他の部分においては、図1に示す半導体素子1000と同様であるのでその詳細な説明を省略する。なお、図4に示す半導体素子1000は、CSPによる実装形態の場合に選択される半導体素子1000の形状である。
図6に示す半導体装置2000は、第1の半導体素子部分100と第2の半導体素子部分200とからなる半導体素子1000と、半導体装置部分500と、外部接続端子600とにより構成される。
再配線層510は、銅又は銅合金により形成される。再配線層510は、パッド接続領域511と、パッド接続領域511に接続される接続領域512と、接続領域512に接続されるポスト形成領域513とにより構成される。再配線層510は絶縁層220上に形成され、一端側であるパッド接続領域511が第2のパッド213と接続される。他端側であるポスト形成領域513は、ポスト520の形成される位置まで延在する。ポスト形成領域513は、ポスト520の径よりも面積の大きい円又は多角形の形状となっている。本実施例では、ポスト形成領域513は八角形の形状となっている。なお、ポスト520が円筒形である場合には、ポスト形成領域511の多角形の形状は八角形以上の多角形とすることによって、上面から見た場合においてポスト520の面積に近付くため、少ない面積でポスト520を形成することが可能となる。再配線層510を有することによって、半導体素子1000の配線層210と半導体装置2000の再配線層510とを用いて、第2のパッド213及びポスト520の位置を任意に設定することができる。すなわち、第1のパッド211の位置に対してポスト形成領域513の位置を接続部212と接続領域512とを用いて任意に設定することが可能となる。この場合、配線層210の抵抗値よりも再配線層510の抵抗値の方が低いため、リセット信号やデータ信号を入出力する端子においては、1又は0の値を読み取ることができればよいことから、接続部212の距離よりも接続領域512の距離が小さくなる、すなわち抵抗値が大きくなってしまう設定も選択することが可能となり、電源端子や接地端子のように一定の電位が必要となる端子においては、電圧の降下は好ましくないことから、接続部212の距離よりも接続領域512の距離を大きくすることによって抵抗値を小さくする設定に制限することが可能となる。このようにして、端子の機能に応じて接続部212の長さと接続領域512の長さとによって第1のパッド211から端子までの抵抗値を調整することが可能となる。
ポスト520は、銅又は銅合金により形成される。ポスト520は、再配線層510のポスト形成領域511上に形成され、円筒形状に形成されている。
封止層530は、ポリイミドなどの樹脂により形成される。封止層530は、絶縁層220上及び再配線層510上に形成され、ポスト520の上面を露出して形成される。
110、3100 半導体層
120、3200 第1の層間絶縁膜
121、3210 第1のコンタクトホール
122、3220 第1のコンタクト電極
130、3300 第2の層間絶縁膜
131、3310 第1の内部配線
132、3320 第2のコンタクトホール
133、3330 第2のコンタクト電極
140、3400 第3の層間絶縁膜
141、3410 第2の内部配線
142、3440 内部回路
143、3420 第3のコンタクトホール
144、3430 第3のコンタクト電極
200 第2の半導体素子部分
210、3500 配線層
211、3510 第1のパッド
212、3520 接続部
213、3530 第2のパッド
220、3600 絶縁層
300、700 搭載基板
310、710 電極
400 ボンディングワイヤ
500 半導体装置部分
510、3700 再配線層
511、3710 パッド接続領域
512、3720 接続領域
513、3730 ポスト形成領域
520、3740 ポスト
530、3750 封止層
600、3760 外部接続端子
1000 半導体素子
2000 半導体装置
Claims (13)
- 内部回路、該内部回路と電気的に接続された電極、及び該内部回路を覆い、該電極を露出して設けられた第1の絶縁層が設けられた第1の半導体素子部分と、
前記電極と電気的に接続されるとともに前記第1の絶縁層上に形成され、第1のパッド及び第2のパッドを有する配線層、及び該第1のパッドと該第2のパッドのいずれか一方を覆い、他方を露出させる第2の絶縁層が設けられた第2の半導体素子部分と、
を有することを特徴とする半導体素子。 - 請求項1に記載の半導体素子において、
前記第1のパッド及び前記第2のパッドは前記第1の絶縁層の上面に形成され、
前記第1のパッドよりも前記第2のパッドの方が前記半導体素子の内側に配置されていることを特徴とする半導体素子。 - 請求項1又は2のいずれか一つに記載の半導体素子において、
前記第2のパッドは前記内部回路の上方に配置されることを特徴とする半導体素子。 - 請求項1乃至請求項3のいずれか一つに記載の半導体素子において、
前記第1のパッドは前記半導体素子の少なくとも一つの端縁近傍に配列されることを特徴とする半導体装置。 - 内部回路、該内部回路と電気的に接続された電極、及び該内部回路を覆い、該電極を露出して設けられた第1の絶縁層が設けられた第1の半導体素子部分と、
前記電極と電気的に接続されるとともに前記第1の絶縁層上に形成され、第1のパッド及び第2のパッドを有する配線層、及び該第1の電極パッドと該第2の電極パッドのいずれか一方を覆い、他方を露出させる第2の絶縁層が設けられた第2の半導体素子部分と、
前記第2の絶縁層上に形成され、前記露出されたパッドと接続された再配線層、該再配線層上に形成され、該再配線層と電気的に接続されるポスト、及び該ポストの一部を露出して、該第2の絶縁膜上に形成される封止層からなる半導体装置部分と、
を有することを特徴とする半導体装置。 - 請求項5に記載の半導体装置において、
前記第1のパッド及び前記第2のパッドは前記第1の絶縁層の上面に形成され、
前記第1のパッドよりも前記第2のパッドの方が前記半導体素子の内側に配置されていることを特徴とする半導体装置。 - 請求項5又は6に記載の半導体装置において、
前記第2のパッドは前記内部回路の上方に配置されることを特徴とする半導体装置。 - 請求項5乃至請求項7のいずれか一つに記載の半導体装置において、
前記第1のパッドは前記半導体装置の少なくとも一つの端縁近傍に配列されることを特徴とする半導体装置。 - 請求項5乃至請求項8のいずれか一つに記載の半導体装置において、
前記配線層は前記第1のパッドと前記第2のパッドとを接続する接続部を有し、
前記再配線層は前記パッドと接続するパッド接続領域、該パッド接続領域に接続される接続領域、該接続領域に接続されるポスト形成領域を有し、
データ信号の入出力に用いられる前記第1のパッドに電気的に接続される前記配線層及び再配線層は、該配線層の接続部の長さよりも該再配線層の接続領域の長さが短いことを特徴とする半導体装置。 - 請求項5乃至請求項9のいずれか一つに記載の半導体装置において、
前記配線層は前記第1のパッドと前記第2のパッドとを接続する接続部を有し、
前記再配線層は前記パッドと接続するパッド接続領域、該パッド接続領域に接続される接続領域、該接続領域に接続されるポスト形成領域を有し、
電源電圧又は接地電圧に用いられる前記第1のパッドに電気的に接続される前記配線層及び再配線層は、該配線層の接続部の長さよりも該再配線層の接続領域の長さが長いことを特徴とする半導体装置。 - 請求項5乃至請求項10のいずれか一つに記載の半導体装置において、
前記ポストは前記半導体装置の外周に沿って規則的に配列され、
前記第1のパッド及び前記第2のパッドは、前記半導体装置の一つの辺に沿って配列されたポストの端部を結ぶ仮想直線上または該仮想直線よりも内側に配置されることを特徴とする半導体装置。 - (方法)
内部回路、該内部回路と電気的に接続された電極、及び該内部回路を覆い、該電極を露出して設けられた第1の絶縁層が設けられた半導体基板を準備する工程と、
前記電極と電気的に接続され、第1のパッド及び第2のパッドを有する配線層を前記第1の絶縁層上に形成する工程と、
目的とする実装態様に応じて前記第1のパッド又は前記第2のパッドのいずれか一方を露出させて形成される第2の絶縁層を前記半導体基板上に形成する工程と、
を有することを特徴とする半導体素子の製造方法。 - 請求項12に記載の半導体素子を用いて半導体装置を製造する方法であって、
前記第2の絶縁層上に前記パッドに接続する再配線層を形成する工程と、
前記再配線層上にポストを形成する工程と、
前記半導体素子上に封止樹脂を形成する工程と、
前記封止樹脂から露出されたポスト上に外部端子を形成する工程と
を有することを特徴とする半導体装置の製造方法。
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