JP2009096655A5 - - Google Patents

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Publication number
JP2009096655A5
JP2009096655A5 JP2007268305A JP2007268305A JP2009096655A5 JP 2009096655 A5 JP2009096655 A5 JP 2009096655A5 JP 2007268305 A JP2007268305 A JP 2007268305A JP 2007268305 A JP2007268305 A JP 2007268305A JP 2009096655 A5 JP2009096655 A5 JP 2009096655A5
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JP
Japan
Prior art keywords
layer
support substrate
nitride
compound semiconductor
substrate
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JP2007268305A
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English (en)
Japanese (ja)
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JP5163045B2 (ja
JP2009096655A (ja
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Publication of JP2009096655A5 publication Critical patent/JP2009096655A5/ja
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JP2007268305A 2007-10-15 2007-10-15 エピタキシャル成長基板の製造方法及び窒化物系化合物半導体素子の製造方法 Expired - Fee Related JP5163045B2 (ja)

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Application Number Priority Date Filing Date Title
JP2007268305A JP5163045B2 (ja) 2007-10-15 2007-10-15 エピタキシャル成長基板の製造方法及び窒化物系化合物半導体素子の製造方法

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Application Number Priority Date Filing Date Title
JP2007268305A JP5163045B2 (ja) 2007-10-15 2007-10-15 エピタキシャル成長基板の製造方法及び窒化物系化合物半導体素子の製造方法

Publications (3)

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JP2009096655A JP2009096655A (ja) 2009-05-07
JP2009096655A5 true JP2009096655A5 (enExample) 2010-12-02
JP5163045B2 JP5163045B2 (ja) 2013-03-13

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JP2007268305A Expired - Fee Related JP5163045B2 (ja) 2007-10-15 2007-10-15 エピタキシャル成長基板の製造方法及び窒化物系化合物半導体素子の製造方法

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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4996448B2 (ja) * 2007-12-25 2012-08-08 パナソニック株式会社 半導体基板の作成方法
JP5491116B2 (ja) * 2009-09-25 2014-05-14 日本碍子株式会社 半導体素子用エピタキシャル基板、半導体素子、および半導体素子用エピタキシャル基板の製造方法
EP2362412B1 (en) 2010-02-19 2020-04-08 Samsung Electronics Co., Ltd. Method of growing nitride semiconductor
JP5059205B2 (ja) 2011-03-03 2012-10-24 株式会社東芝 ウェーハ及び結晶成長方法
KR101773091B1 (ko) * 2011-05-20 2017-08-30 엘지이노텍 주식회사 발광 소자 및 그 제조 방법
JP5891650B2 (ja) * 2011-08-18 2016-03-23 富士通株式会社 化合物半導体装置及びその製造方法
JP6185398B2 (ja) * 2014-01-31 2017-08-23 東京エレクトロン株式会社 窒化ガリウム系結晶の成長方法及び熱処理装置
JP6556664B2 (ja) * 2015-07-08 2019-08-07 クアーズテック株式会社 窒化物半導体基板
JP6288187B2 (ja) * 2016-08-22 2018-03-07 富士通株式会社 化合物半導体装置及びその製造方法
US11515408B2 (en) 2020-03-02 2022-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Rough buffer layer for group III-V devices on silicon
KR102591149B1 (ko) * 2021-12-20 2023-10-19 웨이브로드 주식회사 비발광 3족 질화물 반도체 적층체를 제조하는 방법
CN113540295B (zh) * 2021-06-23 2023-07-21 山西中科潞安紫外光电科技有限公司 一种氮化铝衬底模板的制作方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5393993A (en) * 1993-12-13 1995-02-28 Cree Research, Inc. Buffer structure between silicon carbide and gallium nitride and resulting semiconductor devices
JP2001122693A (ja) * 1999-10-22 2001-05-08 Nec Corp 結晶成長用下地基板およびこれを用いた基板の製造方法
JP2007246289A (ja) * 2004-03-11 2007-09-27 Nec Corp 窒化ガリウム系半導体基板の作製方法

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