JP2009076497A5 - - Google Patents

Download PDF

Info

Publication number
JP2009076497A5
JP2009076497A5 JP2007241375A JP2007241375A JP2009076497A5 JP 2009076497 A5 JP2009076497 A5 JP 2009076497A5 JP 2007241375 A JP2007241375 A JP 2007241375A JP 2007241375 A JP2007241375 A JP 2007241375A JP 2009076497 A5 JP2009076497 A5 JP 2009076497A5
Authority
JP
Japan
Prior art keywords
wiring pattern
metal layer
semiconductor
forming
support plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007241375A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009076497A (ja
JP5064158B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from JP2007241375A external-priority patent/JP5064158B2/ja
Priority to JP2007241375A priority Critical patent/JP5064158B2/ja
Priority to KR1020080089605A priority patent/KR20090029646A/ko
Priority to TW097135581A priority patent/TW200917365A/zh
Priority to US12/212,171 priority patent/US7615408B2/en
Priority to EP08164619.2A priority patent/EP2040294B1/en
Priority to CNA2008101612052A priority patent/CN101393877A/zh
Publication of JP2009076497A publication Critical patent/JP2009076497A/ja
Publication of JP2009076497A5 publication Critical patent/JP2009076497A5/ja
Publication of JP5064158B2 publication Critical patent/JP5064158B2/ja
Application granted granted Critical
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2007241375A 2007-09-18 2007-09-18 半導体装置とその製造方法 Expired - Fee Related JP5064158B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2007241375A JP5064158B2 (ja) 2007-09-18 2007-09-18 半導体装置とその製造方法
KR1020080089605A KR20090029646A (ko) 2007-09-18 2008-09-11 반도체 장치의 제조 방법
TW097135581A TW200917365A (en) 2007-09-18 2008-09-17 Method of manufacturing semiconductor device
US12/212,171 US7615408B2 (en) 2007-09-18 2008-09-17 Method of manufacturing semiconductor device
EP08164619.2A EP2040294B1 (en) 2007-09-18 2008-09-18 Method of manufacturing a semiconductor device
CNA2008101612052A CN101393877A (zh) 2007-09-18 2008-09-18 制造半导体器件的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007241375A JP5064158B2 (ja) 2007-09-18 2007-09-18 半導体装置とその製造方法

Publications (3)

Publication Number Publication Date
JP2009076497A JP2009076497A (ja) 2009-04-09
JP2009076497A5 true JP2009076497A5 (enrdf_load_stackoverflow) 2010-09-02
JP5064158B2 JP5064158B2 (ja) 2012-10-31

Family

ID=40227776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007241375A Expired - Fee Related JP5064158B2 (ja) 2007-09-18 2007-09-18 半導体装置とその製造方法

Country Status (6)

Country Link
US (1) US7615408B2 (enrdf_load_stackoverflow)
EP (1) EP2040294B1 (enrdf_load_stackoverflow)
JP (1) JP5064158B2 (enrdf_load_stackoverflow)
KR (1) KR20090029646A (enrdf_load_stackoverflow)
CN (1) CN101393877A (enrdf_load_stackoverflow)
TW (1) TW200917365A (enrdf_load_stackoverflow)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102246605B (zh) * 2008-12-16 2013-08-07 株式会社村田制作所 电路模块
JP5160498B2 (ja) * 2009-05-20 2013-03-13 ルネサスエレクトロニクス株式会社 半導体装置
JP2011258867A (ja) * 2010-06-11 2011-12-22 Casio Comput Co Ltd 半導体装置及びその製造方法
CN103205701A (zh) * 2012-01-16 2013-07-17 昆山允升吉光电科技有限公司 蒸镀掩模板及其制作方法
US9235674B2 (en) * 2013-03-05 2016-01-12 Oracle International Corporation Mitigating electromigration effects using parallel pillars
WO2016179023A1 (en) * 2015-05-01 2016-11-10 Adarza Biosystems, Inc. Methods and devices for the high-volume production of silicon chips with uniform anti-reflective coatings
US11056410B2 (en) * 2017-03-31 2021-07-06 National Institute Of Advanced Industrial Science And Technology Method of manufacturing semiconductor package using alignment mark on wafer
CN116504645A (zh) * 2023-05-04 2023-07-28 无锡广芯封装基板有限公司 一种封装基板及其制作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0734059B1 (en) 1995-03-24 2005-11-09 Shinko Electric Industries Co., Ltd. Chip sized semiconductor device and a process for making it
JP2843315B1 (ja) * 1997-07-11 1999-01-06 株式会社日立製作所 半導体装置およびその製造方法
US20040061220A1 (en) * 1996-03-22 2004-04-01 Chuichi Miyazaki Semiconductor device and manufacturing method thereof
JPH10256306A (ja) 1997-03-12 1998-09-25 Hitachi Chem Co Ltd 回路板の製造法
US20030001286A1 (en) * 2000-01-28 2003-01-02 Ryoichi Kajiwara Semiconductor package and flip chip bonding method therein
JP3732378B2 (ja) * 2000-03-03 2006-01-05 新光電気工業株式会社 半導体装置の製造方法
JP3638250B2 (ja) * 2000-10-11 2005-04-13 シャープ株式会社 アライメントマークおよび半導体装置の製造方法
JP3614828B2 (ja) * 2002-04-05 2005-01-26 沖電気工業株式会社 チップサイズパッケージの製造方法
JP2004193497A (ja) * 2002-12-13 2004-07-08 Nec Electronics Corp チップサイズパッケージおよびその製造方法
TWI221330B (en) * 2003-08-28 2004-09-21 Phoenix Prec Technology Corp Method for fabricating thermally enhanced semiconductor device
US8067823B2 (en) 2004-11-15 2011-11-29 Stats Chippac, Ltd. Chip scale package having flip chip interconnect on die paddle
JP2006013533A (ja) * 2005-07-28 2006-01-12 Oki Electric Ind Co Ltd 半導体装置
JP2008108849A (ja) 2006-10-24 2008-05-08 Shinko Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
JP2008235555A (ja) 2007-03-20 2008-10-02 Shinko Electric Ind Co Ltd 電子装置の製造方法及び基板及び半導体装置

Similar Documents

Publication Publication Date Title
JP2009076497A5 (enrdf_load_stackoverflow)
TWI331388B (en) Package substrate, method of fabricating the same and chip package
TWI413223B (zh) 嵌埋有半導體元件之封裝基板及其製法
JP2020529742A5 (enrdf_load_stackoverflow)
GB2579325A (en) High-density interconnecting adhesive tape
TWI420630B (zh) 半導體封裝結構與半導體封裝製程
JP2006128455A5 (enrdf_load_stackoverflow)
JP2011003758A5 (enrdf_load_stackoverflow)
JP2008091628A5 (enrdf_load_stackoverflow)
US9258890B2 (en) Support structure for stacked integrated circuit dies
KR101730916B1 (ko) 반도체 패키지 및 그 제조 방법
JP2008084959A5 (enrdf_load_stackoverflow)
KR20130030370A (ko) 패키지 기판 및 이를 갖는 반도체 패키지
TWI503935B (zh) 半導體封裝件及其製法
JP5803345B2 (ja) 半導体チップの製造方法、回路実装体及びその製造方法
JP2007294488A5 (enrdf_load_stackoverflow)
JP2009129982A5 (enrdf_load_stackoverflow)
TWI630665B (zh) 製作晶片封裝結構之方法
US20090166892A1 (en) Circuit board for semiconductor package having a reduced thickness, method for manufacturing the same, and semiconductor package having the same
KR20160042486A (ko) 반도체 패키지 제조용 ncf 및 이의 제조 방법, ncf를 이용한 반도체 패키지 제조 방법
JP2008288481A (ja) 半導体装置およびその製造方法
TW200608532A (en) IC chip solder bump structure and method of manufacturing same
TWI623984B (zh) 封裝結構及其製法
JP2009521815A (ja) 開口部（ベント）を有する柔軟端子の組み込み及び方法
KR100771874B1 (ko) 반도체 탭 패키지 및 그 제조방법