JP2009065182A - 半導体構成素子の製造方法 - Google Patents
半導体構成素子の製造方法 Download PDFInfo
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Abstract
【解決手段】光出射半導体層、又は、光出射半導体素子、2つのコンタクト個所及び垂直又は水平に構造化された支持体基板を有する半導体構成素子の製造方法において、支持体基板は、熱応力を、構成素子が故障しないように十分に小さくし、乃至、補償するように構造化する。
【選択図】なし
Description
0=Σzi Ei di αi T
その際、
ziは、中性軸と素子iとの間の間隔、
Eiは、素子iのフックの弾性率、
diは、素子iの厚み、
αiは、素子iの熱膨張係数、
Tは、構成素子の温度
である。
0≒Σzi Ei di αi T
本発明の、半導体構成素子の製造方法は、ほぼ以下の方法ステップを有している:
(a) 光出射半導体層を成長基板上にエピタキシャル堆積するステップ、
(b) 半導体層に金属コンタクト層を設けるステップ、
(c) 少なくとも金属コンタクト層を介して付着層及びウェット層を形成するステップ、
(d) 機械的に安定な支持体基板を付着層及びウェット層上に堆積、形成又は析出するステップ、
(e) 半導体層を成長基板から分離するステップ、
(f) 各メサ状溝間の各個別チップの定義のために、各メサ溝をエッチングするステップを有しており、その際、各メサ溝は、少なくとも全半導体層及び全コンタクト層に亘って形成されており、
(g) 電気コンタクトを半導体層上に堆積するステップ、
(h) 各メサ溝に沿って分離することによって各チップを個別に切り離すステップ
を有している。
図1は、本発明の製造方法により製造された構成素子の第1の実施例の断面略図、
図2A及びBは、各々、熱応力下での構成素子の断面略図及び曲げられたウエーハの断面略図、
図3A,B及びCは、各々、種々異なる作動条件下での本発明の構成素子の第2の実施例の断面略図、
図4は、本発明の製造方法により製造された構成素子の第3の実施例の断面略図、
図5は、本発明の製造方法により製造された構成素子の第4の実施例の断面略図、
図6A及びBは、各々種々異なる作動条件下での本発明の構成素子の第5の実施例の断面略図、
図7A〜7Gは、本発明の方法の第1の実施例の幾つかの方法ステップの断面略図、
図8は、本発明の構成素子の第6の実施例の断面略図、
図9A〜9Fは、本発明の方法の第2の実施例の幾つかの方法ステップの断面略図、
図10A〜10Gは、本発明の方法の第3の実施例の幾つかの方法ステップの断面略図、
図11A〜11Dは、本発明の方法の第4の実施例の幾つかの方法ステップの断面略図、
図12A及び12Bは、各々、第4の方法による実施例の組み立て方法を断面略図で示した図、
図13A及び13Bは、本発明の方法の第5の実施例の幾つかの方法ステップの断面略図
を示す。
Claims (38)
- 光出射半導体構成素子の製造方法において、
以下の方法ステップ:
(a) 光出射半導体層(2)を成長基板(1)上にエピタキシャル堆積するステップ、
(b) 前記半導体層(2)に金属コンタクト層(3)を設けるステップ、
(ba) 各メサ溝(10)間に各個別チップを定義するために前記メサ溝(10)をエッチングするステップであって、前記メサ溝(10)を少なくとも全半導体層(2)及び全金属コンタクト層(3)によって形成するステップ、
(c) 少なくとも前記金属コンタクト層(3)を介して付着層及びウェット層(6)を形成するステップ、
(d) 機械的に安定な支持体基板(7)を付着層及び前記ウェット層(6)上に堆積、形成又は析出し、
感光性レジストを前記ウェット層(6)上に堆積し、相応に一貫して構造化して、1つ又は複数のネガティブの型を、垂直の各構造素子(25)によって形成し、
支持体基板を、前記ネガティブの型内、及び、感光性レジスト上に当該感光性レジストの上側の支持体ベース(24)の形成に至る迄堆積するステップ、
(e) 前記半導体層(2)を前記成長基板(1)から分離するステップ、
(f) 電気半導体層(2)上を前記半導体層(2)上に堆積するステップ、
(g) 前記各メサ溝(10)に沿って分離することによって前記各チップを個別に切り離すステップ
を有していることを特徴とする光出射半導体構成素子の製造方法。 - 感光性レジストを選択的に取り除き、感光性レジストの除去により生じる中間スペースを、支持体基板(7)の材料よりも弾性的である充填材料(27)で充填し、又は、感光性レジストを、支持体基板(7)の材料よりも弾性的である充填材料として用いる請求項1記載の方法。
- 方法ステップ(b)により、反射層(4)をコンタクト層(3)上に堆積するか、又は、コンタクト層(3)内に集積する請求項1又は2記載の方法。
- 拡散障壁部(5)を反射層(4)上に堆積する請求項3記載の方法。
- コンタクト層を方法ステップ(b)により、反射層(4)、拡散障壁部(5)、ウェット層(6)を方法ステップ(c)により、及び/又は、コンタクト(8)を方法ステップ(f)により、スパッタリング又は蒸着を用いて堆積する請求項1から4迄の何れか1記載の方法。
- 選択的に溶解可能な材料を成長基板(1)に使用し、
方法ステップ(e)による半導体層(2)の、前記成長基板(1)からの切離しを、前記成長基板(1)の選択的なエッチングによって行う請求項1から5迄の何れか1記載の方法。 - 方法ステップ(a)の前に、選択的に溶解可能な材料製の犠牲層を、成長基板上に堆積し、その結果、方法ステップ(a)を是近畿犠牲層上で行い、
方法ステップ(e)による半導体層(2)の、成長基板(1)からの切離しを前記犠牲層の選択的なエッチングによって行う請求項1から6迄の何れか1記載の方法。 - 予めラミネートされた基板を成長基板(1)として使用し、前記ラミネートされた基板が、適切な目標破断個所を有する付着層を有しており、前記破断個所で、方法ステップ(e)の間、成長基板(1)を所期のように前記半導体層(2)から切り離す請求項1から6迄の何れか1記載の方法。
- 方法ステップ(e)による、半導体基板(2)の、成長基板(1)からの切離しを、レーザリフトオフ方法によって行い、前記半導体層(2)を、成長基板(1)との境界面でレーザを用いて分解する請求項1から6迄の何れか1記載の方法。
- 機械的に安定な支持体基板(7)を、スパッタリング方法、CVD方法、ガルバニックによる方法又は電流レスのメッキによって析出する請求項1から9迄の何れか1記載の方法。
- 方法ステップ(d)により、支持体基板(7)上に、付加的な補助基板(12)を堆積する請求項1から10迄の何れか1記載の方法。
- 付加的な補助基板(12)を、支持体基板(7)上に接着剤方法又はハンダ・ロウ付けを用いて取り付ける請求項11記載の方法。
- ハンダ・ロウ付けに必要なハンダ・ロウ層(11)及び/又は補助基板(12)を、スパッタリング、蒸着又はガルバニックにより堆積する請求項12記載の方法。
- 支持体基板(7)及び場合によっては補助基板(12)及びハンダ・ロウ付け又は接着層(11)の全厚みが、15μmを超過しないようにする請求項1から13迄の何れか1記載の方法。
- 方法ステップ(f)による、半導体層(2)上へのコンタクト(8)の堆積後、パッシベーション層(9)を少なくとも部分的に半導体層(2)上に堆積する請求項1から14迄の何れか1記載の方法。
- 方法ステップ(f)による、半導体層(2)上へのコンタクト(8)の堆積後、3次元構造を、半導体層(2)上、及び/又は、パッシベーション層(9)が設けられている場合には当該パッシベーション層(9)上での光出力結合を最適化するために3次元構造を堆積する請求項1から15迄の何れか1記載の方法。
- 3次元構造を、光出力結合の最適化のために、ピラミッド状に、ピラミッド毎に少なくとも3つの可視面と共に半導体層(2)、及び/又は、パッシベーション層(9)上に、又は、円錐状に前記半導体層(2)上及び/又は前記パッシベーション層(9)上に形成する請求項16記載の方法。
- 3次元構造を光出力結合の最適化のためにウェットエッチング又はドライエッチングを用いて形成する請求項16又は17記載の方法。
- 方法ステップ(b)により、パッシベーション層(9)を少なくとも部分的に半導体層(2)、コンタクト層(3)上に、及び、反射層(4)、拡散障壁部(5)が設けられている場合、当該反射層(4)及び当該拡散障壁部(5)上に堆積する請求項1から18迄の何れか1記載の方法。
- 方法ステップ(g)により、チップをソーイング又はレーザ切断により切り離す請求項1から19迄の何れか1記載の方法。
- 方法ステップ(c)により、メサ溝(10)内にウェット層(6)上に切り離しウェブ(13)を堆積して、当該切離しウェブ(13)が前記メサ溝(10)を全長に亘って完全に充填し、前記各切離しウェブ間に位置している前記ウェット層(6)の表面から突出するようにする請求項1から20迄の何れか1記載の方法。
- 切り離しウェブ(13)を、少なくとも10μmの高さに溝ベース上に堆積する請求項21記載の方法。
- 感光性レジストを切り離しウェブ(13)用の材料として使う請求項21又は22記載の方法。
- 切離しウェブを、フォトリソグラフィ又はLIGA方法を用いて堆積する請求項21から23迄の何れか1記載の方法。
- 切離しウェブ(13)を、横断面が尖塔部を有するように形成する請求項21から24迄の何れか1記載の方法。
- 方法ステップ(d)を、単に各切離しウェブ(13)間のスペース内で行い、支持体基板材料を、前記切離しウェブ(13)の高さに迄堆積する請求項21から25迄の何れか1記載の方法。
- 方法ステップ(d)を、単に、各切離しウェブ(13)間のスペース内で行い、支持体基板材料を前記切離しウェブ(13)の高さを超過する迄堆積する請求項21から25迄の何れか1記載の方法。
- 方法ステップ(f)により、半導体層(2)上にコンタクト(8)を堆積した後に、切離しウェブ(13)の材料を選択的に取り除く請求項27記載の方法。
- 切離しウェブ(13)の材料を、溶剤を用いて溶解する請求項28記載の方法。
- 方法ステップ(g)でのチップの切離しを、切断プロセスを用いて実行する請求項27から29迄の何れか1記載の方法。
- 方法ステップ(h)の間、チップをストライプ(17)に切離し、当該ストライプ(17)から、切り離し及びボンディング工具(18)を用いて取り付ける請求項27から30迄の何れか1記載の方法。
- 方法ステップ(e)の前に、切離しウェブ(13)の材料を選択的に切り離し、坦体基板の島(71)を形成し、
その後、成長基板(1)の上側の全構造を、拘束されていない、突出した坦体基板島(71)及びメサ溝(10)を含み、補助材料(14)から完全に成形し、
方法ステップ(g)でのチップの切離しを実行し、坦体薄板(15)を各電気コンタクト(8)を介して半導体層(2)上に堆積し、補助材料(14)を選択的に取り除く請求項26記載の方法。 - 金属、ポリマー及び/又はガラスに基づく材料を補助材料(14)として使う請求項32記載の方法。
- 方法ステップ(c)による付着及びウェット層(6)の堆積を、単に外側の層の表面上に限定し、
方法ステップ(d)の前に、測定溝(10)を完全にアンチウェット層(16)で被覆し、
方法ステップ(d)による坦体基板(7)の堆積を、相応に、付着及びウェット層(6)上にだけ行い、隣接の坦体基板島(71)の一緒の成長前に停止し、
成長基板(1)の上側の全構造を、突出した自由坦体基板島(71)及びメサ溝(10)を含めて、補助材料(14)によって完全に成形し、
方法ステップ(g)でのチップの切離しを実行し、坦体薄板(15)を電気コンタクト(8)を介して半導体層(2)上に堆積し、補助材料(14)を選択的に取り除く請求項1から20迄の何れか1記載の方法。 - 感光性レジストを選択的に取り除く請求項1〜34迄の何れか1記載の方法。
- 感光性レジストの除去により
生じる中間スペース(26)を、充填材料(27)で充填する請求項35記載の方法。 - 充填材料(27)を弾性的に支持体基板(7)の材料として用いる請求項36記載の方法。
- 感光性レジストを構造化して、垂直構造素子の少なくとも1つのネガティブの型を、半導体層(2)の中央部の下側に設ける請求項1から37迄の何れか1記載の方法。
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Also Published As
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DE10245631A1 (de) | 2004-04-15 |
TW200406934A (en) | 2004-05-01 |
CN101373808A (zh) | 2009-02-25 |
CN101373808B (zh) | 2010-10-13 |
US20070181891A1 (en) | 2007-08-09 |
JP5183413B2 (ja) | 2013-04-17 |
WO2004032247A3 (de) | 2004-09-02 |
DE10245631B4 (de) | 2022-01-20 |
CN1685531A (zh) | 2005-10-19 |
CN100440550C (zh) | 2008-12-03 |
TWI240428B (en) | 2005-09-21 |
US20060065905A1 (en) | 2006-03-30 |
US7557381B2 (en) | 2009-07-07 |
JP2006516066A (ja) | 2006-06-15 |
US7208337B2 (en) | 2007-04-24 |
WO2004032247A2 (de) | 2004-04-15 |
EP1547162B1 (de) | 2015-03-04 |
JP4230455B2 (ja) | 2009-02-25 |
EP1547162A2 (de) | 2005-06-29 |
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