JP2008532292A - フリップ・チップ・デバイスを形成するための構造および方法 - Google Patents

フリップ・チップ・デバイスを形成するための構造および方法 Download PDF

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Publication number
JP2008532292A
JP2008532292A JP2007557202A JP2007557202A JP2008532292A JP 2008532292 A JP2008532292 A JP 2008532292A JP 2007557202 A JP2007557202 A JP 2007557202A JP 2007557202 A JP2007557202 A JP 2007557202A JP 2008532292 A JP2008532292 A JP 2008532292A
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JP
Japan
Prior art keywords
conductive
forming
pad
bump
base metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007557202A
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English (en)
Japanese (ja)
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JP2008532292A5 (enExample
Inventor
バッチマン，マーク，アダム
ビッティング，ドナルド，ステーブン
チェイサー，ダニエル，パトリック
クック，タエホー
マーチャント，サイレッシュ，マンシン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agere Systems LLC
Original Assignee
Agere Systems LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems LLC filed Critical Agere Systems LLC
Publication of JP2008532292A publication Critical patent/JP2008532292A/ja
Publication of JP2008532292A5 publication Critical patent/JP2008532292A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/281—Auxiliary members
    • H10W72/283—Reinforcing structures, e.g. bump collars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
JP2007557202A 2005-02-24 2006-02-24 フリップ・チップ・デバイスを形成するための構造および方法 Pending JP2008532292A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US65581605P 2005-02-24 2005-02-24
PCT/US2006/006673 WO2006091856A1 (en) 2005-02-24 2006-02-24 Structure and method for fabricating flip chip devices

Publications (2)

Publication Number Publication Date
JP2008532292A true JP2008532292A (ja) 2008-08-14
JP2008532292A5 JP2008532292A5 (enExample) 2009-04-16

Family

ID=36370840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007557202A Pending JP2008532292A (ja) 2005-02-24 2006-02-24 フリップ・チップ・デバイスを形成するための構造および方法

Country Status (6)

Country Link
US (1) US7777333B2 (enExample)
JP (1) JP2008532292A (enExample)
KR (1) KR101266335B1 (enExample)
CN (1) CN100593232C (enExample)
GB (1) GB2438788B (enExample)
WO (1) WO2006091856A1 (enExample)

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* Cited by examiner, † Cited by third party
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KR100886710B1 (ko) 2007-07-27 2009-03-04 주식회사 하이닉스반도체 반도체 패키지 및 이의 제조 방법
TWI392070B (zh) * 2008-05-05 2013-04-01 欣興電子股份有限公司 半導體元件暨嵌埋有半導體元件之封裝基板及其製法
JP5361264B2 (ja) 2008-07-04 2013-12-04 ローム株式会社 半導体装置
US7985671B2 (en) * 2008-12-29 2011-07-26 International Business Machines Corporation Structures and methods for improving solder bump connections in semiconductor devices
US8405211B2 (en) 2009-05-08 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Bump pad structure
KR101167805B1 (ko) 2011-04-25 2012-07-25 삼성전기주식회사 패키지 기판 및 이의 제조방법
US9905524B2 (en) * 2011-07-29 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures in semiconductor device and packaging assembly
US8580672B2 (en) * 2011-10-25 2013-11-12 Globalfoundries Inc. Methods of forming bump structures that include a protection layer
KR101890711B1 (ko) * 2012-05-03 2018-08-22 에스케이하이닉스 주식회사 범프 버퍼 스프링패드부를 포함하는 전자 소자의 패키지 및 제조 방법
WO2014071815A1 (zh) * 2012-11-08 2014-05-15 南通富士通微电子股份有限公司 半导体器件及其形成方法
US9379077B2 (en) 2012-11-08 2016-06-28 Nantong Fujitsu Microelectronics Co., Ltd. Metal contact for semiconductor device
CN102915986B (zh) 2012-11-08 2015-04-01 南通富士通微电子股份有限公司 芯片封装结构
US9269682B2 (en) * 2013-02-27 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure
TWI517328B (zh) 2013-03-07 2016-01-11 矽品精密工業股份有限公司 半導體裝置
US20150279793A1 (en) * 2014-03-27 2015-10-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9802813B2 (en) * 2014-12-24 2017-10-31 Stmicroelectronics (Malta) Ltd Wafer level package for a MEMS sensor device and corresponding manufacturing process
US10591687B2 (en) 2017-05-19 2020-03-17 Adolite Inc. Optical interconnect modules with 3D polymer waveguide
US10608158B2 (en) * 2017-09-29 2020-03-31 International Business Machines Corporation Two-component bump metallization
US10727391B2 (en) 2017-09-29 2020-07-28 International Business Machines Corporation Bump bonded cryogenic chip carrier
US10535698B2 (en) * 2017-11-28 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Image sensor with pad structure
CN108323009A (zh) * 2018-01-11 2018-07-24 南昌黑鲨科技有限公司 器件结构及器件布局
US11018103B2 (en) * 2019-09-19 2021-05-25 Nanya Technology Corporation Integrated circuit structure
CN112786467B (zh) * 2019-11-07 2025-04-11 长鑫存储技术有限公司 半导体结构、制备方法及半导体封装结构
US11233024B2 (en) * 2019-12-23 2022-01-25 Micron Technology, Inc. Methods for forming substrate terminal pads, related terminal pads and substrates and assemblies incorporating such terminal pads

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49112570A (enExample) * 1973-02-23 1974-10-26
US20030216039A1 (en) * 2002-05-17 2003-11-20 Taiwan Semiconductor Manufacturing Company Method for fabricating an under bump metallization structure
JP2004055855A (ja) * 2002-07-19 2004-02-19 Toyoda Gosei Co Ltd 通信装置
WO2004059708A2 (en) * 2002-12-20 2004-07-15 Agere Systems Inc. Structure and method for bonding to copper interconnect structures

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462426B1 (en) * 2000-12-14 2002-10-08 National Semiconductor Corporation Barrier pad for wafer level chip scale packages
KR100640576B1 (ko) * 2000-12-26 2006-10-31 삼성전자주식회사 유비엠의 형성방법 및 그에 의해 형성된 반도체 소자
JP4656275B2 (ja) * 2001-01-15 2011-03-23 日本電気株式会社 半導体装置の製造方法
US6426281B1 (en) * 2001-01-16 2002-07-30 Taiwan Semiconductor Manufacturing Company Method to form bump in bumping technology
DE10146353B4 (de) * 2001-09-20 2007-08-16 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Lötperle und Lötperlenstruktur
US7470997B2 (en) * 2003-07-23 2008-12-30 Megica Corporation Wirebond pad for semiconductor chip or wafer
JP2008016514A (ja) * 2006-07-03 2008-01-24 Renesas Technology Corp 半導体装置の製造方法および半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49112570A (enExample) * 1973-02-23 1974-10-26
US20030216039A1 (en) * 2002-05-17 2003-11-20 Taiwan Semiconductor Manufacturing Company Method for fabricating an under bump metallization structure
JP2004055855A (ja) * 2002-07-19 2004-02-19 Toyoda Gosei Co Ltd 通信装置
WO2004059708A2 (en) * 2002-12-20 2004-07-15 Agere Systems Inc. Structure and method for bonding to copper interconnect structures

Also Published As

Publication number Publication date
CN100593232C (zh) 2010-03-03
US20090072393A1 (en) 2009-03-19
KR20070104919A (ko) 2007-10-29
GB2438788A (en) 2007-12-05
GB2438788B (en) 2009-03-11
WO2006091856A1 (en) 2006-08-31
US7777333B2 (en) 2010-08-17
KR101266335B1 (ko) 2013-05-24
GB0718502D0 (en) 2007-10-31
CN101128926A (zh) 2008-02-20

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