JP2008529358A - 反比例するプロセス依存参照電流を使用してスルーレート制御する出力バッファ - Google Patents
反比例するプロセス依存参照電流を使用してスルーレート制御する出力バッファ Download PDFInfo
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- JP2008529358A JP2008529358A JP2007552213A JP2007552213A JP2008529358A JP 2008529358 A JP2008529358 A JP 2008529358A JP 2007552213 A JP2007552213 A JP 2007552213A JP 2007552213 A JP2007552213 A JP 2007552213A JP 2008529358 A JP2008529358 A JP 2008529358A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018557—Coupling arrangements; Impedance matching circuits
- H03K19/018571—Coupling arrangements; Impedance matching circuits of complementary type, e.g. CMOS
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- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Dram (AREA)
- Electronic Switches (AREA)
- Amplifiers (AREA)
Abstract
Description
スルーレート制御を行う1つの手法としては、出力スルーレートを正確に示す出力バッファの複製回路を構築することが挙げられる。
次に、スルーレート制御電流は、複製スルーレートの測定値が範囲内になるまで調整される。
Iout=(VIO/2)×(1/REXT)×(1/N)=VIO/4000
である。
Avが大きい場合、入力がゲートの増幅器のしきい値に到達する前のスルーレートは、
Claims (10)
- 集積回路の出力ドライバーのスルーレートの変動を低減する方法であって、
第1のパフォーマンス依存電流(805)を生成するステップ、
参照電流(801)を生成するステップ、
前記参照電流および前記パフォーマンス依存性電流を用いたパフォーマンスに反比例する第3電流(860)を生成するステップ、および、
前記出力ドライバーの一部を形成する第1トランジスタ回路(817)のゲートへ前記第3電流を供給しこれにより前記スルーレートを制御するステップを含む、方法。 - 前記パフォーマンスの向上は、プロセスおよび電圧の変動のうちの少なくとも一方に起因するものである、請求項1に記載の方法。
- 前記第3電流を生成するために、前記参照電流から前記パフォーマンス依存電流を減算するステップを更に含む、請求項1あるいは2のいずれかに記載の方法。
- 前記参照電流および第2パフォーマンス依存電流を使用して第4電流(862)を生成するステップ、および、
前記出力ドライバーの一部を形成する第2トランジスタ回路(811)のゲートへ前記第4電流を供給するステップ、を含む、請求項1から3のいずれかに記載の方法。 - 出力回路から出力されるデータが第1の値であるときに、前記集積回路の出力端子を第1電源ノードに接続する第1トランジスタ(817)を含む出力回路(207)を含み、前記第1トランジスタは前記出力回路のパフォーマンスに反比例した第1ゲート電流(860)を受信するように結合されている、集積回路。
- パフォーマンスの変動は、プロセス変動、電圧変動、および温度変動の少なくとも1つに起因する、請求項5に記載の集積回路。
- 前記出力回路のパフォーマンスに反比例した第2ゲート電流をそのゲートで受信するように結合された第2トランジスタ(811)を更に含み、前記第2トランジスタは前記データが第2の値であるときに、前記出力端子を第2電源ノードに接続する、請求項5あるいは6のいずれかに記載の集積回路。
- 前記パフォーマンスに反比例した第1電流を供給する第1電流源と、
参照電流を供給する第2電流源と、を更に含み、
前記ゲート電流は前記第1電流と前記参照電流とを組み合わせることで生成される、請求項5から7のいずれかに記載の集積回路。 - 外部抵抗(301)と前記集積回路(303)の出力端子における電圧とによって決定される電流値に比例した参照電流に対応する電流を生成する電流ミラーリング(315)を更に含む、請求項8に記載の集積回路。
- 前記出力回路はさらに、前記出力回路の出力が所与の出力値に到達後、前記第1のゲート電流を増加するように結合された1つ以上の付加的トランジスタ(851、853)を含む、請求項5から9のいずれかに記載の集積回路。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/038,909 | 2005-01-20 | ||
US11/038,909 US7521975B2 (en) | 2005-01-20 | 2005-01-20 | Output buffer with slew rate control utilizing an inverse process dependent current reference |
PCT/US2006/001595 WO2006078649A1 (en) | 2005-01-20 | 2006-01-17 | Output buffer with slew rate control utilizing an inverse process dependent current reference |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008529358A true JP2008529358A (ja) | 2008-07-31 |
JP5043682B2 JP5043682B2 (ja) | 2012-10-10 |
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Application Number | Title | Priority Date | Filing Date |
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JP2007552213A Active JP5043682B2 (ja) | 2005-01-20 | 2006-01-17 | 反比例するプロセス依存参照電流を使用してスルーレート制御する出力バッファ |
Country Status (8)
Country | Link |
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US (1) | US7521975B2 (ja) |
JP (1) | JP5043682B2 (ja) |
KR (1) | KR101196871B1 (ja) |
CN (1) | CN101107779B (ja) |
DE (1) | DE112006000251B4 (ja) |
GB (1) | GB2438104B (ja) |
TW (1) | TWI377790B (ja) |
WO (1) | WO2006078649A1 (ja) |
Families Citing this family (13)
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US7991369B2 (en) | 2006-09-26 | 2011-08-02 | Silicon Laboratories Inc. | Reducing power dissipation using process corner information |
US7902885B2 (en) * | 2006-12-28 | 2011-03-08 | Stmicroelectronics Pvt. Ltd. | Compensated output buffer for improving slew control rate |
CN101325362B (zh) * | 2008-04-15 | 2010-07-21 | 福州大学 | 无短路损耗的cmos缓冲器驱动电路 |
US7911262B2 (en) * | 2009-03-29 | 2011-03-22 | Nanya Technology Corp. | External compensation for input current source |
US9176558B2 (en) * | 2009-09-29 | 2015-11-03 | Silicon Laboratories Inc. | Optimizing bias points for a semiconductor device |
US8154322B2 (en) * | 2009-12-21 | 2012-04-10 | Analog Devices, Inc. | Apparatus and method for HDMI transmission |
US7928769B1 (en) * | 2010-03-25 | 2011-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Logic circuits with current control mechanisms |
US8344793B2 (en) * | 2011-01-06 | 2013-01-01 | Rf Micro Devices, Inc. | Method of generating multiple current sources from a single reference resistor |
US8736357B2 (en) | 2011-02-28 | 2014-05-27 | Rf Micro Devices, Inc. | Method of generating multiple current sources from a single reference resistor |
US8508304B2 (en) * | 2011-10-17 | 2013-08-13 | Texas Instruments Incorporated | Serdes VCO with phased outputs driving frequency to voltage converter |
US8922254B2 (en) * | 2013-01-29 | 2014-12-30 | Macronix International Co., Ltd. | Drive circuitry compensated for manufacturing and environmental variation |
US9444462B2 (en) | 2014-08-13 | 2016-09-13 | Macronix International Co., Ltd. | Stabilization of output timing delay |
US9419596B2 (en) | 2014-09-05 | 2016-08-16 | Macronix International Co., Ltd. | Sense amplifier with improved margin |
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JP2002353803A (ja) * | 2001-03-27 | 2002-12-06 | Texas Instruments Inc | 温度補償スルーレート制御回路 |
JP2003087110A (ja) * | 2001-09-17 | 2003-03-20 | Mitsubishi Electric Corp | 半導体回路装置 |
JP2004282783A (ja) * | 1992-07-15 | 2004-10-07 | Natl Semiconductor Corp <Ns> | 制御型スルーレート出力バッファ |
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EP0678983B1 (en) | 1994-04-22 | 1998-08-26 | STMicroelectronics S.r.l. | Output buffer current slew rate control integrated circuit |
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- 2005-01-20 US US11/038,909 patent/US7521975B2/en active Active
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- 2006-01-17 JP JP2007552213A patent/JP5043682B2/ja active Active
- 2006-01-17 CN CN2006800027402A patent/CN101107779B/zh active Active
- 2006-01-17 TW TW095101679A patent/TWI377790B/zh active
- 2006-01-17 DE DE112006000251.1T patent/DE112006000251B4/de active Active
- 2006-01-17 KR KR1020077016417A patent/KR101196871B1/ko active IP Right Grant
- 2006-01-17 WO PCT/US2006/001595 patent/WO2006078649A1/en active Application Filing
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- 2007-07-16 GB GB0713747A patent/GB2438104B/en active Active
Patent Citations (5)
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JP2004282783A (ja) * | 1992-07-15 | 2004-10-07 | Natl Semiconductor Corp <Ns> | 制御型スルーレート出力バッファ |
JPH0936673A (ja) * | 1994-12-16 | 1997-02-07 | Sgs Thomson Microelectron Inc | 補償済のバイアス電圧を与える回路 |
JPH09237493A (ja) * | 1995-09-20 | 1997-09-09 | Texas Instr Inc <Ti> | 温度及び供給電圧補償出力バッファー |
JP2002353803A (ja) * | 2001-03-27 | 2002-12-06 | Texas Instruments Inc | 温度補償スルーレート制御回路 |
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Also Published As
Publication number | Publication date |
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TWI377790B (en) | 2012-11-21 |
JP5043682B2 (ja) | 2012-10-10 |
CN101107779B (zh) | 2010-10-27 |
GB2438104B (en) | 2009-12-02 |
KR101196871B1 (ko) | 2012-11-01 |
DE112006000251B4 (de) | 2017-11-02 |
CN101107779A (zh) | 2008-01-16 |
WO2006078649A1 (en) | 2006-07-27 |
DE112006000251T5 (de) | 2008-02-07 |
GB2438104A (en) | 2007-11-14 |
KR20070095954A (ko) | 2007-10-01 |
US7521975B2 (en) | 2009-04-21 |
TW200642270A (en) | 2006-12-01 |
GB0713747D0 (en) | 2007-08-22 |
US20060190880A1 (en) | 2006-08-24 |
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